Multiple columns for high-throughput complementary e-beam lithography (CEBL)

Shape positional accuracy is a ubiquitous challenge when writing critical features using electron beam (e-beam) lithography. Positional accuracy can be particularly important when patterning for dense pattern arrays often found in plasmonic device structures. These arrays contain structures critically placed within a few tens or hundreds of nanometers apart from one another, whereby poor positional accuracy on the same order of magnitude would impact overall device performance. The sources of positional accuracy are varied on an e-beam lithography system and can include, but are not limited to beam drift, surface charging, environmental noise, and temperature to name a few. This work demonstrates the impact of shape writing order on sub-100 nm features to tolerate these potential sources of shape positional errors. The shape positional accuracy of both proximity effect corrected (PEC) and non-PEC array patterns are studied using a 20 MHz fixed clock 50 keV Gaussian spot electron beam lithography system exposing at 1 nA with a 60 μm final aperture, and a 20 nm beam step size using 200 nm of ZEP520A from ZEON Chemicals atop a bulk Si substrate. The patterns are transferred via etch or metal deposition. The authors find that both pattern design and data preparation impacts positional accuracy by way of the designed shape order or the reshuffling of shapes, respectively. Resorting the shapes within the arrays allows the beam to continuously raster or meander through the array along the X- or Y-axis, row by row or column-by-column, respectively, while exposing abutting shapes yields optimal shape placement with a negligible impact on writing time.

We describe a method for characterizing field stitching in e-beam lithography systems. The method, which is based upon the moiré principle, enables one to measure interfield stitching errors to the nanometer level using only a conventional optical microscope. The technique is more sensitive than the commonly used vernier method, and it does not require the use of a coordinate-measuring tool. Our experiments show that this technique can determine the interfield stitching to within 2 nm.

We report the nanofabrication and characterization of x-ray transmission gratings with a high aspect ratio and a feature size of down to 65 nm. Two nanofabrication methods, the combination of electron beam and optical lithography and the combination of electron beam, x-ray, and optical lithography, are presented in detail. In the former approach, the proximity effect of electron beam lithography based on a thin membrane of low-z material was investigated, and the x-ray transmission gratings with a line density of up to 6666 lines/mm were demonstrated. In the latter approach, which is suitable for low volume production, we investigated the x-ray mask pattern correction during the electron beam lithography process and the diffraction effect between the mask and wafer during the x-ray lithography process, and we demonstrated the precise control ability of line width and vertical side-wall profile. A large number of x-ray transmission gratings with a line density of 5000 lines/mm and Au absorber thickness of up to 580 nm were fabricated. The optical characterization results of the fabricated x-ray transmission gratings were given, suggesting that these two reliable approaches also promote the development of x-ray diffractive optical elements.

High resolution optical lithography or high throughput electron beam lithography: The technical struggle from the micro to the nano-fabrication evolution

Nano-patterns fabricated with extreme ultraviolet (EUV) or electron-beam (E-beam) lithography exhibit unexpected variations in size. This variation has been attributed to statistical fluctuations in the number of photons/electrons arriving at a given nano-region arising from shot-noise (SN). The SN varies inversely to the square root of a number of photons/electrons. For a fixed dosage, the SN is larger in EUV and E-beam lithographies than for traditional (193 nm) optical lithography. Bottom-up and top-down patterning approaches are combined to minimize the effects of shot noise in nano-hole patterning. Specifically, an amino-silane surfactant self-assembles on a silicon wafer that is subsequently spin-coated with a 100 nm film of a PMMA-based E-beam photoresist. Exposure to the E-beam and the subsequent development uncover the underlying surfactant film at the bottoms of the holes. Dipping the wafer in a suspension of negatively charged, citrate-capped, 20 nm gold nanoparticles (GNP) deposits one particle per hole. The exposed positively charged surfactant film in the hole electrostatically funnels the negatively charged nanoparticle to the center of an exposed hole, which permanently fixes the positional registry. Next, by heating near the glass transition temperature of the photoresist polymer, the photoresist film reflows and engulfs the nanoparticles. This process erases the holes affected by SN but leaves the deposited GNPs locked in place by strong electrostatic binding. Treatment with oxygen plasma exposes the GNPs by etching a thin layer of the photoresist. Wet-etching the exposed GNPs with a solution of I2/KI yields uniform holes located at the center of indentations patterned by E-beam lithography. The experiments presented show that the approach reduces the variation in the size of the holes caused by SN from 35% to below 10%. The method extends the patterning limits of transistor contact holes to below 20 nm.

Hybrid lithography based fabrication of 3D patterns by deep reactive ion etching

Charged particle lithography comprises lithographic patterning techniques in which the imaging action is mediated by charged particles such as electrons (as in electron-beam lithography) and ions (as in ion-beam lithography). Some of the key concepts and methods employed in these lithographies are similar to those of optical lithography. However, there are some distinct differences between each of the lithographies that make up charged particle lithography, as well as between them and those that make up optical lithography. In the following sections, we explore these differences in more detail, from the point of view of how they are implemented as a lithographic strategy. We start with electronbeam lithography and end with ion-beam lithography. 15.2 Electron-Beam Lithography Electron-beam lithography (EBL) refers to a lithographic patterning technique in which a focused beam of electrons is used to expose and pattern resist-coated semiconductor substrates as part of a number of steps used in the fabrication of IC devices. Its introduction into IC fabrication dates back to 1957.1 Today, electron-beam lithography is used primarily in fabrication of masks used in optical lithography and x-ray lithography. It is also used in low-volume fabrication of exploratory IC device layers with extremely small features; it has also found application in nanotechnology research. Like photons, electrons exhibit particle and wavelike properties, but their wavelength (0.012-0.024 nm, corresponding to 50-100-keV of energy for electrons used in EBL) is three orders of magnitude shorter than the wavelength of UV radiation used in optical lithographic exposure tools, and hence their resolution is not limited by diffraction. Only features with atomic-scale dimensions are able to diffract electron beams. Electron-beam lithography therefore has the potential for extremely high resolution. In fact, features as small as 10 nm have been successfully fabricated with electron-beam lithography. In addition, electron beams image with extremely large depth of focus, providing relief from one of the most challenging problems of optical lithography.

Nanostructures of silicon are becoming increasingly important as they may combine new opto-electronic features or devices with CMOS technology. This enables the integration of e.g. nanowire sensors with readout electronics or nanoscale LEDs grown directly on Si wafers. A problem here is that nanostructures are often fabricated using a bottom-up approach necessitating a second deposition step of random nature or involving a tedious alignment procedure. This is because current lithography techniques do not allow sub 10 nm precision for direct top-down fabrication. In this presentation I will show examples of fabricating some generic silicon structures such as nanowires, nanopores and quantum dots using optical or e-beam lithography where a second process step is used to shrink feature sizes in a controlled way. Thus, the lithography step for positioning of nanostructures and the size determining process step become decoupled, as shown by three examples from our work: (i) Silicon nanowires were fabricated using a top-down approach using optical lithography. Thinning of the device layer to ∼20 nm enabled picomolar sensitivity for detection of biomolecules, avoiding traditional CVD growth of nanowires. These “nanoribbons” allows multiple parallel detection and direct electrical readout. (ii) Nanopores are interesting for single molecule detection and DNA sequencing. We have fabricated silicon membranes with arrays of nanopores down to sub 10 nm diameter. Electro-chemical etching was used as the final size control. This allows multiple optical detection of DNA translocation. (iii) Finally, individual Si quantum dots have been fabricated using e-beam lithography and a final tuning of the core by oxidation in a “self-limiting” regime. This has allowed single-dot spectroscopy revealing quantum confined exciton recombination with ultra-sharp emission lines. Many other features such as blinking and spectral diffusion have been observed, similar to direct bandgap quantum dots. Recent data indicate that very high quantum yields are possible enabling new applications.

In this work, we first fabricated the conventional metal-semiconductor-metal (MSM) interdigitated electron detector with aluminum contact as the control group, then used e-beam lithography system and reactive ion etcher (RIE) to fabricate aluminum nano-rod array structure on the contact area and used RIE to fabricate the periodic rectangle trench in the active area of the electron detector as another MSM interdigitated electron detector at the same time as the experimental group. According to the experimental data, we found that the MSM electron detectors with aluminum nano-rod array and periodic trench structure had better electricity characteristic and performance as directly illuminated and secondary electron detector.

A physical method of reducing feature size and proximity effects in sub-quarter-micrometer e-beam lithography is described. A thin layer (50 to 300 nm) of silicon nitride deposited on a semiconductor substrate, prior to resist deposition, has been found to enhance the resist resolution. The samples were patterned with a 50-keV, 15-nm-diam probe generated by a JEOL JBX-5Dll e-beam lithography system. Point spread function measurements in 60-nm-thick SAL-601 on Si are shown to illustrate the resolution enhancement in the nanolithographic regime (sub-100 nm). The technique has been applied to lithography on 400-nm-thick W films, such as would be used in x-ray mask fabrication. The 200 nm of SAL-601 was spun onto W film samples, which were half-coated with 200 nm of silicon nitride. Identical lithographic patterns were written on each half of the sample. On examination of the samples after postexposure processing and development, reduced feature sizes and proximity effects were seen on the sample half with the silicon nitride intermediary layer. For example, in a field effect transistor (FET) type pattern, with a coded 500-nm gap between the source and drain pads, the gate could only be successfully resolved when the intermediary nitride layer was present. Monte Carlo simulations were performed on a CM-200 connection machine. The results show a large number of fast secondary electrons are generated within a 100-nm radius of the incident electron beam. The implications of fast secondary electrons on resolution in e-beam lithography are discussed. The total number of fast secondary electrons entering the resist is reduced by the silicon nitride layer. Simulations compare the thin-layer technique to a bilayer resist technique, used to improve resolution at larger dimensions.

Quantum optical lithography from 1nm resolution to pattern transfer on silicon wafer

Electron-beam (E-beam) lithography has been applied to porous silicon substrates. In contrast with optical lithography, the whole process is fully compatible with the material, without any need for particular previous treatments. Porous silicon behaves as a low density substrate, allowing fine writing even at moderate electron energies, with a negligible proximity effect. High quality structures are expected if films deposited on porous silicon are defined by the E-beam, as in the case of freestanding membranes. Patterns written at lower resolution have been successfully transferred to porous silicon using plasma etching techniques. This allows the possibility of direct lateral structuring of porous silicon, a key factor in the realization of high quality devices for photonics. © 2003 The Electrochemical Society. All rights reserved.

State-of-the-art diffractive optical elements (DOEs) and computer generated holograms (CGHs) are fabricated using e-beam lithography and dry etching techniques to achieve multi-level phase elements with very high diffraction efficiencies. Electron beam lithography allows DOEs/CGHs with smaller feature sizes (e.g. for off-axis diffractive lenses with small f-number) to be fabricated. Dry etching techniques, especially chemically assisted reactive ion beam, allows DOEs/CGHs be fabricated in a variety of materials. Multi-level phase DOEs/CGHs, especially those of sixteen or more phase levels, mean their surface profiles are fabricated with high accuracy / quality. It is not only the e-beam system which dictates the feature size limitations, but also the alignment systems (mask aligner) and the materials (e-beam or photo resists). In order to allow DOEs/CGHs to be used in new optoelectronic systems, it is necessary also to fabricate the elements in different materials economically. Since the cost of a multi-level phase DOE/CGH is determined by the e-beam writing time, the number of etching steps for fabricating the master, and the technology for replication, we need to decrease the writing time and etching steps for the master and to develop a low cost replication technology for mass production without affecting the quality of the DOEs/CGHs. In this Chapter, we will review three DOE/CGH fabrication techniques and CAD development required, considering the overall design and fabrication time for multi-level phase DOEs.

Summary form only given. Nanoscale metal-semiconductor-metal (MSM) photodetectors and MESFETs are key elements in ultra-fast optical and wireless communication systems. However, devices with sub-0.25 /spl mu/m feature sizes are typically fabricated using electron-beam lithography (EEL), which has high cost and low throughput. Nanoimprint lithography (NIL), on the other hand, has both low cost and high throughput, as well as sub-l0 nm resolution. We report the fabrication of MSM photodetectors on semi-insulating (SI) GaAs using NIL, and the examination of NIL on the quality of the nanoscale Schottky contact. We found that if the imprint pressure is 600 psi or lower, nanoscale GaAs MSM photodetectors fabricated using NIL are comparable to those fabricated by conventional EEL and photolithography, indicating no degradation to the photodetector Schottky contact induced by the imprint process.

In order to fabricate submicron pattern, total electron beam (EB) lithography system has been developed. Upper submicron pattern will be realized by optical lithography, which requires reticle with high accuracy. An EB writing system, EBM-130/40, has the performance of drawing capability of 4 M bit DRAM reticle pattern in about 40 minutes. The EB system incorporated with peripheral technologies including data compaction conversion software, reticle inspection system, APC-130R, and EBR-9 resist process can produce advanced reticles of number of about 600 per month. For lower submicron pattern formation, next generation lithography system is required. The EBM-130V is the variable shaped EB system with high acceleration voltage of 50 kV and high dosage of 50 μC/cm² for direct writing and X-ray mask fabrication for development of the high bit density VLSI pattern. This system makes possible EB/optical combined lithography. Its metrology function allows it to measure X-ray mask distortion.