Multiprocessors and Asynchronous Event Handling in the Real-Time Specification for Java

The primary goal for asynchronous event handling (AEH) in the Real-Time Specification for Java (RTSJ) is to have a lightweight concurrency mechanism. However the RTSJ neither provides a well-defined guideline on how to implement AEH nor requires the documentation of the AEH model used in the implementation. Also the AEH API in the RTSJ are criticized as lacking in configurability as they do not provide any means for programmers to have fine control over the AEH facilities, such as the mapping between real-time threads and handlers. For these reasons, it needs the refactoring of its application programming interface (API) to give programmers more configurability. This paper, therefore, proposes a set of AEH related classes and interfaces to enable flexible configurability over AEH components. We have implemented the refactored configurable AEH API using the new specifications on an existing RTSJ implementation and this paper shows that it allows more configurability for programmers than the current AEH API in the RTSJ does. Consequently programmers are able to specifically tailor the AEH subsystem to fit their applicationspsila particular needs.

The OSGi Framework, has proven ideal in developing dynamically reconfigurable Java applications based on the principles of Component-Based Software Engineering (CBSE) and Service-Oriented Architecture (SOA). One domain where OSGi has yet to make an impact is real-time systems. This is partly due to the fact that the OSGi Framework is based on standard Java, which is not suitable for developing such systems. Other reasons include the absence of various features such as temporal isolation, admission control, and a reconfigurable garbage collector (along with the associated analysis to determine the pace of garbage collection). Also, a number of features of the OSGi Framework increase the difficulty in determining the worst case execution time (WCET) of threads. This makes real-time analysis more difficult. This chapter discusses the problems associated with extending the OSGi Framework and integrating it with the Real-Time Specification for Java (RTSJ). The focus is on the design of a real-time version of the OSGi Framework (RT-OSGi) which is capable of deploying dynamically reconfigurable real-time Java applications.

: There is an increasing interest in recent years to use the Java(trade mark) programming language for implementing real-time systems. Recent advances in the Real-Time Specification for Java (RTSJ) have resulted in the introduction of new means for creating predictable real-time environments for Java programs. However, these new features also make the Java semantics more complex and the run-time behaviors of the Java programs more difficult to analyze. In this technical report, we describe a number of preliminary experiments we performed to study the features of the Sun Java Real-Time System (RTJ 1.0). We designed these experiments to verify the viability of the Real-Time Java language for the implementation of the Global Integrated Fire Control System (GIFC)-a component of the C2BMC element of the Ballistic Missile Defense System (BMDS). Our preliminary experiment shows that it is preferable to use only the Real-Time Java threads that use the heap memory and not the no-heap real-time threads for the GIFC software. However, such architecture cannot be implemented by using RTJ 1.0. Further experiments are needed to determine if the preferred architecture can be implemented with the upcoming RTJ 2.0, which will give programmers more control over the priority of the garbage collection.

An algorithm for load balancing in multiprocessor systems

Smartphone and tablet “apps” are particularly susceptible to asynchrony bugs. In order to maintain responsive user interfaces, events are handled asynchronously. Unexpected schedules of event handlers can result in apparently-random bugs which are notoriously difficult to reproduce, even given the user-event sequences that trigger them. We develop the AsyncDroid tool for the systematic discovery and reproduction of asynchrony bugs in Android apps. Given an app and a user-event sequence, AsyncDroid systematically executes alternate schedules of the same asynchronous event handlers, according to a programmable schedule enumerator. The input user-event sequence is given either by user interaction, or can be generated by automated ui “monkeys”. By exposing and controlling the factors which influence the scheduling order of asynchronous handlers, our programmable enumerators can explicate reproducible schedules harboring bugs. By enumerating all schedules within a limited threshold of reordering, we maximize the likelihood of encountering asynchrony bugs, according to prevailing hypotheses in the literature, and discover several bugs in Android apps found in the wild.

In the consensus problem in a system with n processes, each process starts with a private input value and has to choose irrevocably a decision value, which was the input value of some process of the system; moreover, all processes have to decide on the same value. This work deals with the problem of wait-free-fully resilient to processor crash and napping failures-consensus of n processes in an in-phase multiprocessor system. It proves the existence of a solution to the problem, in this system by presenting a protocol which ensures that each process will reach decision within at most n(n-3)/2+3 steps of its own in the worst case, or within n steps if no process fails.

The functionality of embedded systems is ever growing. The computational power of embedded systems is growing to match this demand, with embedded multiprocessor systems becoming more common. The limitations of embedded systems are not always related to chip size but are commonly due to energy and/or power constraints. While it can be possible to embed a more powerful Multiprocessor System on Chip (MPSoC), it is not always possible to provide an energy or power supply that meets its demands within the device’s size and weight requirements. Power management through Dynamic Voltage and Frequency Scaling (DVFS) enables the device to be run at less than its maximum voltage and frequency, allowing high computational capability when necessary while conserving power at other times. Embedded systems commonly perform real-time functionality. A real-time application has an associated formal model to verify that it meets its timing requirements. This formal model is used to perform a worst-case timing analysis to ensure that the application meets its requirements. These models incorporate the worst-case timing of the application’s computation and communication. Timing changes due to power management must also be taken into account, complicating the verification process. The drive for evermore functionality has led to mixed time-criticality systems, in which multiple applications of various timing criticalities share the same (hardware) resources. This complicates the verification process further as the timing interference due to shared resource contention must be taken into account. A monolithic verification effort is therefore traditionally required after system integration and must be carried out again if any modifications are made that affect the timing of any of the applications. The problem that we aim to solve in this work is to enable real-time applications to perform independent execution and power management without violating their timing requirements or invalidating the timing verification of concurrently executing applications. To solve this problem, we contribute the Composable and Predictable Microkernel (CoMik) to composably and predictably virtualise processors. When used in combination with composable and predictable memory controllers and interconnect (as provided by the Composable and Predictable System-on-Chip (CompSOC) platform), these virtual processors cannot interfere with each other’s timing by even a single cycle. If whatever executes on the virtual processors (e.g. an Operating System (OS) or an application directly) has a real-time requirement, it can be verified independently of whatever executes on the concurrent virtual processors and other virtual resources. To enable formally analysable application execution, we contribute the Predictable Operating System (POSe) that enables dataflow applications to be executed on the (virtualised) processor. We contribute a combined application and platform dataflow graph, including an algorithm to automate this process. When annotated with worst-case timings, the combined application and system graph is then used to verify that the application meets its timing requirement. If the application’s performance is better than its requirement (e.g. when the input or platform behaviour are better than worst case), its performance can be reduced using DVFS to achieve a reduction in power consumption. We contribute an off-line convex optimisation that uses the combined application and platform dataflow model to derive static run-time operating frequency levels to achieve low power consumption. The off-line technique is able to exploit static slack in the schedule, but not dynamic run-time slack due to variations in task execution times. Before dynamic slack can be used it must be possible to observe it. For this purpose, CoMik provides independent power, energy and timing accounting per virtual processor. This enables each virtual processor to be assigned individual power and energy budgets and POSe applications to be assigned timing budgets. We contribute a description and model of how energy and power budgets can be distributed between multiple virtual processors, enabling whatever executes on the virtual processor to perform composable independent power-management without affecting the ability of other virtual processors from using their entire budget allocation. Using CoMik’s accounting infrastructure, we also demonstrate how the quality of applications can be dynamically scaled to assist meeting timing, energy or power requirements. We further contribute a distributed dynamic power management policy that enables dataflow applications that are mapped onto multiple (virtual) processors to make distributed dynamic slack observations and local power-management decisions. We demonstrate the applicability of the presented techniques on an implemented Field Programmable Gate Array (FPGA) prototype of a CompSOC hardware platform instance, using an H.263 decoder as a case-study application. We show that our techniques do not only work in theory, but that they are also implementable and implemented.

We study the problem of scheduling periodic-time-critical tasks on a multiprocessor system. A periodic-time-critical task consists of a certain number of computations, each arising at a fixed interval of time, called the period of the task. The ratio of the computation time to the period is called the utilization factor of the task. Each computation has a prescribed deadline which must be guaranteed to be met, failing which there is likely to result an irrepairable loss. The scheduling problem is to specify the processor on which a computation is to be made and the order in which such computations will be made, such that every computation meets its deadline. The goal is to minimize the number of processors needed. The problem is NP-complete. As such, we devise a heuristic algorithm and analyze its performance. The algorithm assigns tasks based on the utilization factors of the tasks. We analyze the worst case performance of the algorithm by obtaining bounds on the ratio of the maximum number of processors needed by the algorithm to the minimum number of processors required. It is shown that this ratio is 2.

The need for fusion energy depends strongly on fusion's potential to achieve ambitious safety goals more completely or more economically than fission can. The history and present complexion of public opinion about environment and safety gives little basis for expecting either that these concerns will prove to be a passing fad or that the public will make demands for zero risk that no energy source can meet. Hazard indices based on “worst case” accidents and exposures should be used as design tools to promote combinations of fusion-reactor materials and configurations that bring the worst cases down to levels small compared to the hazards people tolerate from electricity at the point of end use. It may well be possible, by building such safety into fusion from the ground up, to accomplish this goal at costs competitive with other inexhaustible electricity sources. Indeed, the still rising and ultimately indeterminate costs of meeting safety and environmental requirements in nonbreeder fission reactors and coal-burning power plants mean that fusion reactors meeting ambitious safety goals may be able to compete economically with these “interim” electricity sources as well.

Chapter 5 - The relative power of primitive synchronization operations

Multiprocessor systems are increasingly becoming the systems of choice for low and high-end servers, running such diverse tasks as number crunching, large-scale simulations, data base engines and world wide web server applications. With such diverse workloads, system utilization and throughput, as well as execution time become important performance metrics. In this paper we present efficient kernel scheduling policies and propose a new kernel-user interface aiming at supporting efficient parallel execution in diverse workload environments. Our approach relies on support for user level threads which are used to exploit parallelism within applications, and a two-level scheduling policy which coordinates the number of resources allocated by the kernel with the number of threads generated by each application. We compare our scheduling policies with the native gang scheduling policy of the IRIX 6.4 operating system on a Silicon Graphics Origin2000. Our experimental results show substantial performance gains in terms of overall workload execution times, individual application execution times, and cache performance.

We describe pipes, a new linguistic mechanism for sequences of ordered asynchronous procedure calls in multiprocessor systems. Pipes allow a sequence of remote invocations to be performed in order, but asynchronously with respect to the calling thread. Using pipes results in programs that are easier to understand and debug than those with explicit synchronization between asynchronous invocations. The semantics of pipes make no assumptions about the underlying architecture, which enhances code portability. However, the implementation of pipes by the language compiler can be optimized so as to take advantage of any underlying message ordering a particular architecture may provide. Pipes also provide application-transparent flow control for asynchronous invocations and are able to throttle invocations from multiple calling threads. We present four implementations of pipes and show that the performance and space overheads associated with pipes are low.

With the increasing use of XML as an information exchange format, there is an increasing need to embed graphics and binary data files within XML documents. This paper describes a technique called substitution and segment-run length encoding (SSRLE) for including binary data in XML documents. Traditional encodings like base 64 and ASCII 85 use a subset of the available printable characters and add considerable space overhead. Alternatives such as packaging and binary XML encodings do not preserve the portability of XML documents. SSRLE uses additional printable characters for substitutions and segment-run lengths to provide savings in terms of the space overhead, with a worst case overhead equal to that of base 64. Our experiments show that SSRLE provides significant space savings for a number of types of different files

Determining order relationship between events of a distributed computation is a fundamental problem in distributed systems which has applications in many areas including debugging, visualization, checkpointing and recovery. Fidge/Mattern’s vector-clock mechanism captures the order relationship using a vector of size N in a system consisting of N processes. As a result, it incurs message and space overhead of N integers. Many distributed applications use synchronous messages for communication. It is therefore natural to ask whether it is possible to reduce the timestamping overhead for such applications. In this paper, we present a new approach for timestamping messages and events of a synchronously ordered computation, that is, when processes communicate using synchronous messages. Our approach depends on decomposing edges in the communication topology into mutually disjoint edge groups such that each edge group either forms a star or a triangle. We show that, to accurately capture the order relationship between synchronous messages, it is sufficient to use one component per edge group in the vector instead of one component per process. Timestamps for events are only slightly bigger than timestamps for messages. Many common communication topologies such as ring, grid and hypercube can be decomposed into $${\lceil N/2 \rceil}$$ edge groups, resulting in almost 50% improvement in both space and communication overheads. We prove that the problem of computing an optimal edge decomposition of a communication topology is NP-complete in general. We also present a heuristic algorithm for computing an edge decomposition whose size is within a factor of two of the optimal. We prove that, in the worst case, it is not possible to timestamp messages of a synchronously ordered computation using a vector containing fewer than $${2 \lfloor N/6 \rfloor}$$ components when N ≥ 2. Finally, we show that messages in a synchronously ordered computation can always be timestamped in an offline manner using a vector of size at most $${\lfloor N/2 \rfloor}$$ .

Bioinformatics applications constitute an emerging data-intensive, high-performance computing (HPC) domain. While there is much research on algorithmic improvements, (2004), the actual performance of an application also depends on how well the program maps to the target hardware. This paper presents a performance study of two parallel bioinformatics applications HMMER (sequence alignment) and SVM-RFE (gene expression analysis), on Intel x86 based hyperthread-capable (2002) shared-memory multiprocessor systems. The performance characteristics varied according to the application and target hardware characteristics. For instance, HMMER is compute intensive and showed better scalability on a 3.0 GHz system versus a 2.2 GHz system. However, SVM-RFE is memory intensive and showed better absolute performance on the 2.2 GHz machine which has better memory bandwidth. The performance is also impacted by processor features, e.g. hyperthreading (HT) (2002) and prefetching. With HMMER we could obtain -75% of the performance with HT enabled with respect to doubling the number of CPUs. While load balancing optimizations can provide speedup of -30% for HMMER on a hyperthreading-enabled system, the load balancing has to adapt to the target number of processors and threads. SVM-RFE benefits differently from the same load-balancing and thread scheduling tuning. We conclude that compiler and runtime optimizations play an important role to achieve the best performance for a given bioinformatics algorithm.