プログラム全域を対象としたホットパスベース投機的マルチスレッド処理方式の提案

The sparse matrix solver has become the bottleneck in a Simulation Program with Integrated Circuit Emphasis circuit simulator. It is difficult to parallelize the sparse matrix solver because of the high data dependence during the numerical LU factorization. In this brief, a parallel LU factorization algorithm is developed on shared-memory computers with multicore central processing units, based on KLU algorithms. An Elimination Scheduler (EScheduler) is proposed to represent the data dependence during the LU factorization. Based on the EScheduler, the parallel tasks are scheduled in two modes to achieve a high level of concurrence, i.e., cluster mode and pipeline mode . The experimental results on 26 circuit matrices reveal that the developed algorithm can achieve speedup of 1.18-4.55t (on geometric average), as compared with KLU, with 1-8 threads. The result analysis indicates that for different data dependence, different parallel strategies should be dynamically selected to obtain optimal performance.

In today’s digital world, image processing plays a crucial role in various aspects of human life. From creating visual content for social media to analyzing medical images, powerful tools for image manipulation are in constant demand. The growing requirements for image quality and processing speed make the search for efficient methods to accelerate these processes highly relevant. This paper investigates the development and implementation of a graphics editor that utilizes OpenMP parallel computing to accelerate data processing. This technology enables the efficient distribution of computational tasks across multiple processor cores, significantly improving system performance. The developed software offers a set of popular graphic effects, including negative, grayscale, sepia, blur, sharpening, and posterization. Each effect is implemented in both sequential and parallel modes using OpenMP, allowing for the comparison of different computational approaches. To evaluate the effectiveness of the proposed solution, a series of experiments were conducted on images of various sizes. These experiments involved applying each effect to images ranging from small icons to high-quality photographs. A comparative analysis of the efficiency of sequential and parallel computation methods demonstrated the significant advantages of the latter. The results of the study show a substantial acceleration of image processing when using OpenMP technology. This acceleration is particularly noticeable for computationally intensive effects such as blurring or sharpening, and when working with large images. In some cases, it was possible to achieve a significant increase in processing speed, opening up new possibilities for working with large volumes of graphic data. This research has significant practical value for software developers working on optimizing the performance of graphics editors and other image processing applications. It demonstrates how the application of modern parallel computing technologies can significantly improve the efficiency of working with graphic data, paving the way for the creation of more powerful and faster image processing tools.

Our aim is to have a high speed and effective control strategy for nonlinear systems such as an inverted pendulum or a robot link system or a legged locomotion robot. The control method by using inverse dynamics compensation is used for controlling of nonlinear systems. But the increase of degrees of freedom would be too much time consuming for calculations of the inverse dynamics. In this paper, we proposed a parallel computing method and control strategies for dynamic systems,especially, nonlinear systems. We tried to develop a DSP based parallel computation and control method and a small DSP unit for installation. The DSP parallel computation enables to realize a high speed calculation of the inverse / forward dynamics. Every module has same calculation routine and can adopt parallel LQ controller proposed in this research. The size of a small DSP unit constructed in our laboratory is (5cm × 6cm).

The area of computing is seeing parallelism increasingly being incorporated at various levels: from the lowest levels of vector processing units following Single Instruction Multiple Data (SIMD) processing, Simultaneous Multi-threading (SMT) architectures, and multi/many-cores with thread-level shared memory and SIMT parallelism, to the higher levels of distributed memory parallelism as in supercomputers and clusters, and scaling them to large distributed systems as server farms and clouds. All together these form a large hierarchy of parallelism. Developing high-performance parallel algorithms and efficient software tools, which make use of the available parallelism, is inevitable in order to harness the raw computational power these emerging systems have to offer. In the work presented in this thesis, we develop architecture-aware parallel techniques on such emerging paradigms in parallel computing, specifically, parallelism offered by the emerging multi- and many-core architectures, as well as the emerging area of cloud computing, to target large scientific applications. First, we develop efficient parallel algorithms to compute optimal pairwise alignments of genomic sequences on heterogeneous multi-core processors, and demonstrate them on the IBM Cell Broadband Engine. Then, we develop parallel techniques for scheduling all-pairs computations on heterogeneous systems, including clusters of Cell processors, and NVIDIA graphics processors. We compare the performance of our strategies on Cell, GPU and Intel Nehalem multi-core processors. Further, we apply our algorithms to specific applications taken from the areas of systems biology, fluid dynamics and materials science: pairwise Mutual Information computations for reconstruction of gene regulatory networks; pairwise Lp-norm distance computations for coherent structures discovery in the design of flapping-wing Micro Air Vehicles, and construction of stochastic models for a set of properties of heterogeneous materials. Lastly, in the area of cloud computing, we propose and develop an abstract framework to enable computations in parallel on large tree structures, to facilitate easy development of a class of scientific applications based on trees. Our framework, in the style of Google's MapReduce paradigm, is based on two generic user-defined functions through which a user writes an application. We implement our framework as a generic programming library for a large cluster of homogeneous multi-core processor, and demonstrate its applicability through two applications: all-k-nearest neighbors computations, and Fast Multipole Method (FMM) based simulations.

Dzięki upowszechnieniu się procesorów wielordzeniowych przetwarzanie danych za pomocą obliczeń równoległych staje się coraz bardziej dostępne dla szerokiego grona użytkowników. Przykładem jest opracowana przez firmę NVIDIA architektura CUDA, będąca architekturą wielordzeniowych procesorów graficznych. Procesor graficzny może być traktowany jako procesor SIMD z pamięcią wspólną. Na przykładzie operacji mnożenia macierzy zbadano wpływ zarządzania pamięcią i blokami wątków na czas obliczeń z użyciem architektury CUDA.

This paper presents a mathematical framework for a family of discrete-time discrete-frequency transforms in terms of matrix signal algebra. The matrix signal algebra is a mathematics environment composed of a signal space, a finite dimensional linear operators and special matrices where algebraic methods are used to generate these signal transforms as computational estimators. The matrix signal algebra contribute to analysis, design and implementation of parallel algorithms in multi-core proccesors. In this work, an implementation and experimental investigation of the mathematical framework are performed using MATLAB r with the Parallel Computing Toolbox TM . We found that there is advantage to use multi-core processors and a parallel computing environment to minimize the high execution time. Also, speedup and efficiency increases when the number of logical processor and length of the signal increase. Moreover, a superlinear speedup is obtained in this ex perimental investigation.

We describe the design, generation, and compression of the extended whole program path (eWPP), representation that not only captures the control flow history of a program execution but also its data dependence history. This representation is motivated by the observation that, typically, a significant fraction of data dependence history can be recovered from the control flow trace. To capture the remainder of the data dependence history, we introduce disambiguation checks in the program whose control flow signatures capture the results of the checks. The resulting extended control flow trace enables the recovery of otherwise irrecoverable data dependences. The code for the checks is designed to minimize the increase in program execution time and the extended control flow trace size when compared to directly collecting control flow and address traces. Our experiments show that compressed eWPPs are only one-quarter of the size of combined compressed control flow and address traces. However, their collection incurs a 5× increase in runtime overhead relative to the overhead required for directly collecting the control flow and address traces, respectively.

Single-instruction-set architecture (Single-ISA) heterogeneous multi-core processors (HMP) are superior to Symmetric Multi-core processors in performance per watt. They are popular in many aspects of the Internet of Things, including mobile multimedia cloud computing platforms. One Single-ISA HMP integrates both fast out-of-order cores and slow simpler cores, while all cores are sharing the same ISA. The quality of service (QoS) is most important for virtual machine (VM) resource management in multimedia mobile computing, particularly in Single-ISA heterogeneous multi-core cloud computing platforms. Therefore, in this paper, we propose a dynamic cloud resource management (DCRM) policy to improve the QoS in multimedia mobile computing. DCRM dynamically and optimally partitions shared resources according to service or application requirements. Moreover, DCRM combines resource-aware VM allocation to maximize the effectiveness of the heterogeneous multi-core cloud platform. The basic idea for this performance improvement is to balance the shared resource allocations with these resources requirements. The experimental results show that DCRM behaves better in both response time and QoS, thus proving that DCRM is good at shared resource management in mobile media cloud computing.

Large-scale packet classification such as Open-Flow table lookup in Software Defined Networking (SDN) is a key task performed at the Internet routers. However, the increasing size of the rule set and the increasing width of each individual rule make large-scale packet classification a challenging problem. In this paper, we present a decomposition-based approach for large-scale packet classification on multicore processors. We develop a model to predict the performance of the classification engine with respect to throughput and latency. This model involves the architectural parameters of the multi-core processors and the design requirements of packet classification. Based on this model, we employ optimization techniques such as grouping short fields in the search phase and early termination of the merge phase. The performance model can be applied to other generic multi-field classification problems as well. To evaluate the accuracy of the performance model, we implement a 15-field classification engine on state-of-the-art multi-core processors. Experimental results show that, the proposed model predicts the performance with less than ±10% error. For a 32 K 15-field rule set, the optimized decomposition-based approach achieves 2000 ns per packet latency and 33 Million Packets Per Second (MPPS) throughput (49% of the peak throughput). The peak performance assumes an ideal execution model that uses an optimized execution sequence and ignores memory access latency, data dependencies, and context switch overhead.

ABSTRACTAs an effective tool for simulating spatiotemporal urban processes in the real world, urban cellular automata (CA) models involve multiple data layers and complicated calibration algorithms, which make their computational capability become a bottleneck. Numerous approaches and techniques have been applied to the development of high-performance urban CA models, among which the integration of vectorization and parallel computing has broad application prospects due to its powerful computational ability and scalability. Unfortunately, this hybrid algorithm becomes inefficient when the axis-aligned bounding box (AABB) of study areas contains many unavailable cells. This paper presents a minimum-volume oriented bounding box (OBB) strategy to solve the above problem. Specifically, geometric transformation (i.e. translation and rotation) is applied to find the OBB of the study area before implementing the hybrid algorithm, and a set of functions are established to describe the spatial coordinate relationship between the AABB and OBB layers. Experiments conducted in this study demonstrate that the OBB strategy can further reduce the computational time of urban CA models after vectorization and parallelism. For example, when the cell size is 15 m and the neighborhood size is 3 × 3, an approximately 10-fold speedup in computational time can result from vectorization in the MATLAB environment, followed by an 18-fold speedup after implementing parallel computing in a quad-core processor and, finally, a speedup of 25-fold by further using an OBB strategy. We thus argue that OBB strategy can make the integration of vectorization and parallel computing more efficient and may provide scalable solutions for significantly improving the applicability of urban CA models.

ABSTRACTAdding the number of computing nodes is a common approach to achieving higher performance in a parallel computing system. However, with constraint of fixed system architecture and fixed algorithm structure, it is difficult to improve the performance of parallel computing only by extending its scale absolutely. To realize such extension with fixed structure, we analyze key factors from architecture and parallel task, which affect the scalability, and then use the weighted graph to model architecture as well as parallel task. Especially, focusing on the case that architecture graph and parallel task graph are homogeneous, we propose the extension method of graph similarity; for the case that architecture graph and parallel task graph are heterogeneous, a critical-path-unchanged scaling method is proposed. Actually, the above two extending methods do not change the graph's structure. They only adjust the node weight and edge-weight in the relevant graph. Furthermore, through mathematical derivation, some conclusions about the new scaling methods are drawn. Finally, in order to verify the effectiveness, some simulative experiments are conducted on the platform SimGrid. The experimental results show that the proposed methods can realize iso-speed-efficiency extension, and can guide practical extensions for parallel computing.

Parallel computing of discrete element method on multi-core processors

As the complexity of software for Cyber-Physical Systems (CPS) rapidly increases, multi-core processors and parallel programming models such as OpenNP become appealing to CPS developers for guaranteeing timeliness. Hence, a parallel task on multi-core processors is expected to become a vital component in CPS such as a self-driving car, where tasks must be scheduled in real-time. In this paper, we extend the fork-join parallel task model to be scheduled in real-time, where the number of parallel threads can vary depending on the physical attributes of the system. To efficiently schedule the proposed task model, we develop the task stretch* transform. Using this transform for global Deadline Monotonic scheduling for fork-join real-time tasks, we achieve a resource augmentation bound of 3.73. In other words, any task set that is feasible on m unit-speed processors can be scheduled by the proposed algorithm on m processors that are 3.73 times faster. The proposed scheme is implemented on Linux/RK as a proof of concept, and ported to Boss, the self-driving vehicle that won the 2007 DARPA Urban Challenge. We evaluate our scheme on Boss by showing its driving quality, i.e., curvature and velocity profiles of the vehicle.

Technology-driven limitations will soon force microprocessor chips to contain multiple processing cores, as the scalability of individual cores peaks while transistor counts continue to increase. To obtain the best performance, flexible management of the on-chip resources, such as cache memory and off-chip bandwidth, is needed. However, the control for the dynamic management of these on-chip resources is difficult to design. In this paper, we propose a method for developing such a controller: evolving a recurrent neural network using the enforced sub-populations algorithm. The method is tested in a trace-based simulation that measures dynamic assignation of a pool of level-two cache banks to a set of processing cores. We present results showing that, when the chip is controlled by the neural network, we obtain a 13% performance improvement over static cache partitioning.

This paper attempts to provide minimization algorithms which are adapted to execution on parallel computers. For this purpose, three well-known nongradient methods are examined. From these, three parallel iterative procedures are derived, by discussing in detail their mathematical behavior, when the cooperating processes are either synchronous or asynchronous.