Network interfaces for programmable NICs and multicore platforms

Our investigation into architectural support for networking tasks began in late 1998, and it began with something of a coincidence. Fiuczynski was an active graduate student participant in the SPIN project at UW [2,3]. He had been writing a SPIN driver for a high-speed network interface card (NIC), and visited Crowley (at the time, a graduate student investigating the relationships between processor & memory architectures and desktop computer applications [4]) one afternoon to discuss the NIC's processor. Had either Fiuczynksi or Crowley been out of the office on that particular day, it is not clear that this collaboration would have emerged. As it happened, both were in the office that day and the NIC processor was very interesting: a dual-core MIPS-like processor built specifically for the NIC. In ensuing discussions, it became clear that-despite the simplicity of its instruction set and microarchitecture-the NIC processor was as a whole more interesting than the much larger and complex x86 processor of the host system. It was more interesting because, as a dual-core processor, it was different and in no way an incremental improvement upon the deeply pipelined CPUs that dominated computing at the time. (They still dominate PCs and servers, of course, but mobile, graphics and embedded chips represent a huge swath of relevant computing platforms today.) It represented evidence of a combination of commercial and technical justification for designing a new and different processor to handle networking tasks.

Although the networking world is still dominated by IP over Ethernet, these protocol suites were not originally designed to work on modern Gigabit or Gigabyte networks. The major problem facing IP at 1 Gb/s and 10 Gb/s speeds is interrupt processing overhead and the resulting low CPU availability for applications. One solution to this problem is to implement endpoint fragmentation on a Network Interface Card (NIC), where an Ethernet driver sends large packets to the NIC and the NIC fragments the packets into frames. This approach reduces interrupt overhead and CPU utilization on the receiver. In order to demonstrate the plausibility of this method, we modified the firmware of Alteon Acenic 2 Gigabit Ethernet cards and the standard Linux (2.4 series) driver to allow the driver to use an MTU of up to 64000 bytes without changing the 9K MTU limitation of the MAC layer. Each datagram is fragmented in the firmware on one end and reassembled in firmware at the other. Our implementation matched peak bandwidth performance of the standard driver and firmware, while demonstrating a significant reduction in CPU utilization.

In multi-channel wireless mesh networks (WMNs), it is significantly important to achieve efficient channel utilization. The channel assignment problem, which investigates how to seek a proper mapping between available channels and network interface cards (NICs) on mesh routers (MRs), is attracting more and more attention from the research community. However, most proposed channel assignment approaches assume that NICs are evenly placed on the MRs, and its amount is also pre-determined. Due to the non-uniform distribution of WMN traffic, the equal interface placement will inevitably cause that the bottleneck MRs suffer from NIC shortage, and MRs with less load only have a low utilization of NICs. Hence, in order to improve network performance and reduce network cost, interface placement should be considered carefully in the process of planning a WMN. In this paper, we investigate the joint interface placement and channel assignment problem, i.e., how to appropriately place NICs on MRs and assign channels to them. We first formulate the problem as a mixed integer linear programming (MILP) model, which aims to minimize the total number of NICs while satisfying logical link, link bandwidth, link interference and traffic demand constraints. Then, we propose an MILP-based heuristic algorithm, using iterated local search to obtain sub-optimal solutions efficiently. Finally, we conduct simulation experiments to compare the heuristic solutions with the optimal solutions, and the results show that our proposed heuristic algorithm can achieve good sub-optimal solutions. Moreover, the simulation results also demonstrate that the algorithm can be well applied in large-scale WMNs where the optimal solutions cannot be obtained, and can perform well under different traffic demands.

As data sets grow rapidly in size and the number, an outlier detection that filters unnecessary normal information becomes important. In this paper, we propose to move the unsupervised outlier detection from an application layer to a network interface card (NIC). Only anomalous items or events are received for a network protocol stack and the other packets are discarded at the NIC. The demands for storage and computation costs at a host are thus dramatically reduced. However, because normal items are discarded at the NIC and the application layer can no longer know what is normal, in our approach, the application at the host periodically peeks at the NIC buffer. We select an outlier detection based on the Mahalanobis distance as one of the simplest algorithms. Our approach is implemented on an FPGA-based NIC that has 10GbE interfaces. The sampling frequency of the NIC buffer vs. outlier detection precision is analyzed. Real experiments using the FPGA NIC demonstrate a 14,000,000 samples-per-second throughput in performance, which is close to the 10GbE line rate.

Many factors can prevent a Gigabit Ethernet network interface card (NIC) from achieving line rate in a modern web server. In fact, the various commercially available NICs have different performance characteristics that lead to throughput differences for actual web servers. For example, Figure 1 shows the performance achieved by the thttpd web server for client traces extracted from the Rice University computer science department (CS), a NASA web site (NASA), and the 1998 soccer World Cup tournament (World Cup). The latter two traces are available from the Internet Traffic Archive (http://ita.ee.lbl.gov/). The server system tested includes an AMD Athlon 2600+ XP processor running the FreeBSD 4.7 operating system, 2 GB of DDR SDRAM, a 64-bit/66 MHz PCI bus, and a single 40 GB IDE disk (none of the workloads are disk intensive). The tested systems differ only in their NIC, with the Intel Pro-1000/MT Server and Desktop, Alteon AceNIC with parallelized firmware [2], Netgear GA622T, 3Com 3C996B, and Alteon AceNIC with released firmware arranged from left to right. There are substantial performance differences across the NICs in the web environment, as the fastest NIC consistently achieves 40–60% more throughput than the slowest. A web server interacts with the network in two primary ways: receiving client HTTP requests and sending HTTP responses. Requests are typically quite small, on the order of 200 bytes of ASCII text, while responses vary from empty files to several hundred megabytes. Since web clients and servers communicate using TCP, the server must acknowledge requests, leading to minimum-sized (64-byte) Ethernet frames. Response data must be segmented and encapsulated in Ethernet frames, which allow up to 1460 bytes of TCP content in a maximum-sized (1518-byte) frame. Then, those segments are sent out according to TCP flow control policies based on the receipt of acknowledgments. A high-performance server NIC must thus support data volumes dominated by sends of large

This chapter examines recent developments in network interface cards (NIC) technology that can be effectively applied by network managers and local area network (LAN) administrators to enhance LAN performance. It provides an overview of the evolution of network adapters and computer bus technology. Most modern NIC designs are based upon the use of shared memory; however, with the introduction of the Peripheral Component Interconnect bus very rarely does a shared memory design achieve anywhere near the theoretical data transfer capability of the bus. The first generation of NICs primarily used I/O ports for data transfer. Although this technique was easy to implement, processor ports are relatively slow, limiting the data transfer capability of the NIC. By the late 1980s, most NIC manufacturers abandoned the use of I/O port data transfer. Shared memory significantly improves the data transfer capability of NICs as data in the NICs’ buffer becomes immediately accessible by the computer.

Always Best Packet Switching (ABPS) is a novel approach for wireless communications that enables mobile nodes, equipped with multiple network interface cards (NICs), to dynamically determine the most appropriate NIC to use. Using ABPS, a mobile node can seamlessly switch to a different NIC in order to get better performance, without causing communication interruptions at the application level. To make this possible, NICs are kept always active and a software monitor constantly probes the channels for available access points. While this ensures maximum connection availability, considerable energy may be wasted when no access points are available for a given NIC. In this paper we address this issue by investigating the use of an "oracle" able to provide information on network availability. This allows to dynamically switch on/off NICs based on reported availability, thus reducing the power consumption. We present a Markov model which allows us to estimate the impact of the oracle on the ABPS mechanism: results show that significant reduction in energy consumption can be achieved with minimal impact on connection availability. We conclude by describing a prototype implementation of the oracle based on Web services and geolocalization.

As data sets grow rapidly in size and the number, an outlier detection that filters unnecessary normal information becomes important. In this paper, we propose to move the outlier detection from an application layer to a NIC (Network Interface Card). Only anomalous items or events are delivered for a network protocol stack and the other packets are discarded at the NIC. The demands for storage and computation costs at a host are thus drastically reduced. We employ lazy learning algorithms for the outlier detection, because they can be applied to complex reference data including different clusters. However, it is challenging to offload the lazy learning to NIC hardware because of high computational cost and huge reference data. In this paper, we propose to cache only a frequently-accessed portion of reference data in the NIC. This idea can be applied to lazy learning algorithms in general. LOF (Local Outlier Factor) and KNN (K-Nearest Neighbor) are thus implemented on an FPGA (Field Programmable Gate Arrays) based NIC. Simulation results of the proposed system using LOF with 100,000 reference data show that 45% to 90% of queries are hit to the proposed cache and filtered at the NIC. The results are corresponding to 1.82x to 10x throughput improvements on the outlier filtering compared to that of a software-based execution.

All smartphones and tablets are currently equipped with Network Interface Cards (NIC) that use IEEE 802.11 family to access Wi-Fi networks or communicate in a peer-to-peer model, which is the topic of this paper. This paper presents a novel technique to detect and isolate a rogue user that modified the firmware on the device's NIC card to capture the channel either to disrupt the communication or to illegally increase its own node throughput in a wireless network with hidden nodes present at the expense of other nodes in the network. The attacker modifies the NIC (Network Card Interface) firmware that is using IEEE 802.11 DCF to deviate from the normal back-off mechanism specified by the IEEE standard which significantly increases the successful probabilities of its packet transmissions. The attacker node only backs off one slot every time it has a packet to transmit or when it experiences a collision. As a result, the attacker captures the channel (Bandwidth) and prevents others from sharing the bandwidth. The attacker forces the NIC to have a firmware upgrade that contains the malicious code. The proposed algorithm detects the attacker in a network with the presence of hidden nodes. The paper's main contributions are: a new method to model Markov Chain to account for the hidden nodes' throughputs, a detection algorithm, and an isolation technique to isolate the attacker.

The performance of microprocessors has increased exponentially for over 35 years. However, process technology challenges, chip power constraints, and difficulty in extracting instruction-level parallelism are conspiring to limit the performance of future individual processors. To address these limits, the computer industry has embraced chip multiprocessing (CMP), predominately in the form of multiple high-performance superscalar processors on the same die. We explore the trade-off between building CMPs from a few high-performance cores or building CMPs from a large number of lower-performance cores and argue that CMPs built from a larger number of lower-performance cores can provide better performance and performance/Watt on many commercial workloads. We examine two multi-threaded CMPs built using a large number of processor cores: Sun's Niagara and Niagara 2 processors. We also explore the programming issues for CMPs with large number of threads. The programming model for these CMPs is similar to the widely used programming model for symmetric multiprocessors (SMPs), but the greatly reduced costs associated with communication of data through the on-chip shared secondary cache allows for more fine-grain parallelism to be effectively exploited by the CMR Finally, we present performance comparisons between Sun's Niagara and more conventional dual-core processors built from large superscalar processor cores. For several key server workloads, Niagara shows significant performance and even more significant performance/Watt advantages over the CMPs built from traditional superscalar processors.

Many distributed applications implement complex data flows and need a flexible mechanism for routing data between producers and consumers. Recent advances in programmable network interface cards, or SmartNICs, represent an opportunity to offload data-flow tasks into the network fabric, thereby freeing the hosts to perform other work. System architects in this space face multiple questions about the best way to leverage SmartNICs as processing elements in data flows. In this paper, we advocate the use of Apache Arrow as a foundation for implementing data-flow tasks on SmartNICs. We report on our experiences adapting a partitioning algorithm for particle data to Apache Arrow and measure the on-card processing performance for the BlueField-2 SmartNIC. Our experiments confirm that the BlueField-2's (de)compression hardware can have a significant impact on in-transit workflows where data must be unpacked, processed, and repacked.

In a wireless mesh network (WMN) with a number of stationary wireless routers, the aggregate capacity can be increased when each router is equipped with multiple network interface cards (NICs) and each NIC is assigned to a distinct orthogonal frequency channel. In this paper, given the logical topology of the network, we mathematically formulate a crosslayer fair bandwidth sharing problem as a non-linear mixedinteger network utility maximization problem. An optimal joint design, based on exact binary linearization techniques, is proposed which leads to a global maximum. A near-optimal joint design, based on approximate dual decomposition techniques, is also proposed which is practical for deployment. Performance is assessed through several numerical examples in terms of network utility, aggregate network throughput, and fairness index. Results show that our proposed designs can lead to multi-channelWMNs which are more efficient and fair compared to their singlechannel counterparts. The performance gain on both efficiency and fairness increase as the number of available NICs per router or the number of available frequency channels increases.

Increasing attention has been recently devoted to software routers based on off-the-shelf hardware and open-source operating systems running on personal computer (PC) architectures. Today's high-end PCs PCI shared buses fit into the multi-gigabit-per-second routing segment, for a price much lower than that of commercial routers. However, commercially available Network Interface Cards (NICs) lack programmability, and require not only packets to cross the PCI bus twice, but also to process them in software by the operating system (OS), reducing routing performance. In this paper we discuss the design of an FPGA-based NIC that permits to overcome the limitations of commercial NICs and provide a detailed description of its implementation.

System component failure – hardware and software, permanent and transient – are an integral part of the life cycle of any computer system. The degree to which a system suffers from these failures depends on factors such as system complexity, system design and implementation, and system size. These errors may lead to catastrophic application failure (termination of an application run with a CPU failure), silent application errors (such as network data corruption), or application hangs (such as when network interface card (NIC) malfunction), all wasting valuable computer time. For certain classes of computer systems, dealing with these failures is a requirement to provide a simulation environment reliable enough to meet end-user needs. Also, the more automated these solutions are, requiring minimal or no end-user intervention, the more likely they are to be used to achieve the required application stability. Dealing with failure, or fault tolerance, while minimizing application performance degradation, is an active research area, with no consensus as to what are optimal solution strategies, or even what failures need to be considered. Errors include items such as transient data transmission errors (dropped or corrupt packets), transient and permanent network failures (NIC), and process failure, to list a few. The current MPI standard addresses a limited number of failure scenarios, with application termination being the default response to failure. While the standard provide a mechanism for users to override this default response, it does not define error codes that provide information on system level failures – hardware or software. None-the-less, these need to be addressed to provide end-users with systems that meet their computing needs. Building on experience gained in the LA-MPI, FT-MPI, and LAM/MPI projects, the Open MPI collaboration has implemented, and is continuing to implement optional solutions that deal with a number of failure scenarios, to decrease the application mean-time-to-failure rate, to acceptable rates. The types of errors currently being dealt with include transient network data transmission errors, transient and permanent NIC failures, and process failure. The talk will discuss fault detection, fault recovery methods, and the degree to which applications need to be modified to benefit fromthese, if any. In addition, the performance impact of these solutions on several applications will be discussed.

Two critical issues impact the overall performance of Linux clusters based on Intel servers: inter-process communication latency and data throughput. Underlying both of these performance challenges is the inefficient use of computational power and server CPU cycles to process the network protocols. Today’s modern high-end Network Interface Cards (NICs) are equipped with an onboard CPU. In most cases, these CPU’s are only used by the vendor and are operated by a proprietary OS, which makes them inaccessible to the HPC application developer. In this paper we present a design and implementation of a framework for building high-performance networking applications. The framework consists of an embedded NIC Operating System with a specialized scheduler. The main challenge in developing such a scheduler is the lack of a preemption mechanism in most high-end NICs. Our scheduler provides finer-grained schedules than the alternatives. We have implemented several network applications, and were able to increase their throughput while decreasing the host’s CPU utilization.KeywordsSchedule AlgorithmHigh Performance ComputingPeriodic TaskNetwork Interface CardHigh Performance Computing ClusterThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.