Neuromorphic Processors with Memristive Synapses

Despite the maturity and availability of speech recognition systems, there are few available spiking speech recognition tasks that can be implemented with current neuromorphic systems. The methods used previously to generate spiking speech data are not capable of encoding speech in real-time or encoding very large modern speech datasets efficiently for input to neuromorphic processors. The ability to efficiently encode audio data to spikes will enable a wider variety of spiking audio datasets to be available and can also enable algorithmic development of real-time neuromorphic automatic speech recognition systems. Therefore, we developed speech2spikes, a simple and efficient audio processing pipeline that encodes recorded audio into spikes and is suitable for real-time operation with low-power neuromorphic processors. To demonstrate the efficacy of our method for audio to spike encoding we show that a small feed-forward spiking neural network trained on data generated with the pipeline achieves accuracy on the Google Speech Commands recognition task, exceeding the state-of-the art set by Spiking Speech Commands, a prior spiking encoding of the Google Speech Commands dataset, by over 10%. We also demonstrate a proof-of-concept real-time neuromorphic automatic speech recognition system using audio encoded with speech2spikes streamed to an Intel Loihi neuromorphic research processor.

Neuromorphic processors aim to emulate the biological principles of the brain to achieve high efficiency with low power consumption. However, the lack of flexibility in most neuromorphic architecture designs results in significant performance loss and inefficient memory usage when mapping various neural network algorithms. This paper proposes SENECA, a digital neuromorphic architecture that balances the trade-offs between flexibility and efficiency using a hierarchical-controlling system. A SENECA core contains two controllers, a flexible controller (RISC-V) and an optimized controller (Loop Buffer). This flexible computational pipeline allows for deploying efficient mapping for various neural networks, on-device learning, and pre-post processing algorithms. The hierarchical-controlling system introduced in SENECA makes it one of the most efficient neuromorphic processors, along with a higher level of programmability. This paper discusses the trade-offs in digital neuromorphic processor design, explains the SENECA architecture, and provides detailed experimental results when deploying various algorithms on the SENECA platform. The experimental results show that the proposed architecture improves energy and area efficiency and illustrates the effect of various trade-offs in algorithm design. A SENECA core consumes 0.47 mm2 when synthesized in the GF-22 nm technology node and consumes around 2.8 pJ per synaptic operation. SENECA architecture scales up by connecting many cores with a network-on-chip. The SENECA platform and the tools used in this project are freely available for academic research upon request.

A long-standing research goal is to develop computing technologies that mimic the brain’s capabilities by implementing computation in electronic systems directly inspired by its structure, function, and operational mechanisms, using low-power, spike-based neural networks. The Loihi neuromorphic processor provides a low-power, large-scale network of programmable silicon neurons for brain-inspired artificial intelligence applications. This paper exploits the Loihi processors and a theory-guided methodology to enable unsupervised learning of spike patterns. Our method ensures efficient and rapid selection of the network’s hyperparameters, enabling the neuromorphic processor to generate attractor states through real-time unsupervised learning. Precisely, we follow a fast design process in which we fine-tune network parameters using mean-field theory. Moreover, we measure the network’s learning ability regarding its error correction and pattern completion aptitude. Finally, we observe the dynamic energy consumption of the neuron cores for each millisecond of simulation equal to 23 μJ/time step during the learning and recall phase for four attractors composed of 512 excitatory neurons and 256 shared inhibitory neurons. This study showcases how large-scale, low-power digital neuromorphic processors can be quickly programmed to enable the autonomous generation of attractor states. These attractors are fundamental computational primitives that theoretical analysis and experimental evidence indicate as versatile and reusable components suitable for a wide range of cognitive tasks.

Linearly potentiated synaptic weight modulation at nanoscale in a highly stable two-terminal memristor

For biological synapses, high sensitivity is crucial for transmitting information quickly and accurately. Compared to biological synapses, memristive ones show a much lower sensitivity to electrical stimuli since much higher voltages are needed to induce synaptic plasticity. Yet, little attention has been paid to enhancing the sensitivity of synaptic devices. Here, electrochemical metallization memory cells based on lightly oxidized ZnS films are found to show highly controllable memristive switching with an ultralow SET voltage of several millivolts, which likely originates from a two-layer structure of ZnS films, i.e., the lightly oxidized and unoxidized layers, where the filament rupture/rejuvenation is confined to the two-layer interface region several nanometers in thickness due to different ion transport rates in these two layers. Based on such devices, an ultrasensitive memristive synapse is realized where the synaptic functions of both short-term plasticity and long-term potentiation are emulated by applying electrical stimuli several millivolts in amplitude, whose sensitivity greatly surpasses that of biological synapses. The dynamic processes of memorizing and forgetting are mimicked through a 5 × 5 memristive synapse array. In addition, the ultralow operating voltage provides another effective solution to the relatively high energy consumption of synaptic devices besides reducing the operating current and pulse width.

Exploration of novel computational platforms is critical for the advancement of artificial intelligence as we approach the physical limitations of traditional hardware. Biologically accurate, energy efficient neuromorphic systems are particularly promising for enabling future breakthroughs because of their ability to process information in parallel and to scale using extremely low power. Sparse coding is a signal processing technique which has been known to model the information encoding in the primary visual cortex. When sparse solutions are solved using local neuron competition along with the unsupervised dictionary learning that mimics cortical development, we can build an end to end, hardware to software, brain inspired solution to a machine learning problem. In this article, we perform a detailed comparison of sparse coding solutions generated classically by orthogonal matching pursuit (OMP) implemented on a conventional digital processor with spike-based solutions obtained using the Intel Loihi neuromorphic processor. A novel “post-hoc” normalization technique to shorten simulation time for Loihi is presented along with analysis of optimal parameter selection, reconstruction errors, and unsupervised dictionary learning for Loihi approaches and their classical counterparts. Preliminary results show that both the Loihi full simulation approach and the post-hoc normalization approach are well suited to neuromorphic processors and operate in a size, weight and power regime that is not accessible by classical approaches. Ultimately, the use of this normalization technique allows for faster and, often, better solutions than demonstrated previously.

Optimizing renewable energy systems for 100 % clean energy target: A comparative study of solar, hydro, pumped hydro, and battery storage technologies

Neuromorphic computing has become an attractive candidate for emerging computing platforms. It requires an architectural perspective, meaning the topology or hyperparameters of a neural network is key to realizing sound accuracy and performance in neural networks. However, these network architectures must be executed on some form of computer processor. For machine learning, this is often done with conventional computer processing units, graphics processor units, or some combination thereof. A neuromorphic computer processor or neuroprocessor, in the context of this paper, is a hardware system that has been designed and optimized for executing neural networks of one flavor or another. Here, we review the history of neuromorphic computing and consider various spiking neuroprocessor designs that have emerged over the years. The aim of this paper is to identify emerging trends and techniques in the design of such brain-inspired neuroprocessor computer systems.

Electrical Double Layer-like Response from Green Synthesized Zirconia Nanoparticles

The potential opportunities for fuel cost and emissions reduction as a result of converting from diesel to natural gas (NG) are well known in the rail industry. Recent developments in domestic sources for petroleum have both lowered the cost and stabilized the natural gas market making the adoption of NG more strategically viable than ever before. NG Engine conversion systems for medium speed diesel engines have been available for over 20 years and environmental incentives are helping to further support the adoption of NG not only as an alternate fuel, but possibly as the new primary fuel. The major challenge for railroad transition to NG is now to develop a manageable and cost effective on board storage architecture with capacity to provide sufficient range to meet industry acceptance for general use. For long haul applications, the solution has been to add a large locomotive NG tender. For short line, switcher and commuter applications, the fuel cost benefits do not warrant the cost and complexity of such a system. For these short to medium range applications, an “on locomotive” storage system with a capacity equivalent to a minimum of 500 diesel gallons is a better solution. This paper summarizes the development of a crashworthy, high capacity, underframe NG storage solution packaged in the form factor normally occupied by the conventional locomotive diesel fuel tank (Fig. 1). Primary challenges for the CNG storage system solution are to achieve high storage density and crashworthiness while within the confines of existing AAR M-1001Plate C profile. It is expected that the system is to meet both the CFR/FRA structural requirements for diesel tanks and relevant DOT requirements for CNG cylinders used in mobile applications. The NG storage system presented consists of an outer enclosure which mounts to the locomotive similarly to the existing diesel fuel tank. The enclosure contains and interfaces with NG cylinders specifically designed for the application. The system design withstands the various load requirements defined in 49 CFR Part 238 Appendix D, that simulate both jackknife derailment and class 8 truck side impact scenarios. NG cylinders within the enclosure must be approved for use in this application and have sufficient capacity and maintainability to create new opportunities for NG conversion in the rail industry. The primary design goal for the storage system is to integrate the cylinder size and configuration within the enclosure such that storage volume is maximized and crash impact loads are minimized. Impact loads are distributed through the system ensuring that point loading sufficient to breach one or more of the NG cylinders or fuel lines does not occur. An overview of the development and results of physical derailment and side impact testing performed in support of this effort are presented.

Semen of the African catfish, Clarias gariepinus (Burchell, 1822), was investigated with respect to its cellular composition, sperm cell density, maturation grade, motility and fertility. Storage conditions were tested, whereby sperm viability was assessed by measurement of the motility after activation and by fertility tests. Testicular semen differed in its composition, i.e. the sperm density and numbers of spermatids, according to the maturity grade of the testis. Two semen types could be distinguished: semen type I was characterized by high sperm densities and low numbers of spermatids and semen type II had lower sperm densities and higher numbers of spermatids. Two semen types did not differ in motility and fertility (when adjusted for differences in sperm density). During storage, the sperm viability was influenced by the sodium concentration of the storage medium, temperature, membrane stabilizers as bovine serum albumen (BSA) or hen egg yolk, antibiotics and oxygen. Semen viability was maintained best when it was diluted at a ratio of 1:5 in storage solution (150 mmol L−1 NaCl, 2.5 mmol L−1 KCl, 1 mmol L−1 CaCl2, 1 mmol L−1 MgSO4, 20 mmol L−1 Tris (pH 8.5) and 0.5% BSA or 0.5% hen egg yolk) and stored at 4 °C. Oxygen gassing and addition of antibiotics (1 mg mL−1 gentamycine sulphate) to the storage solution affected the two semen types in different ways. Antibiotics had no effect on type I semen, but had a positive effect on type II semen. Oxygen gassing had a positive effect on type I semen but a negative effect on type II semen.

Lithium‐ion batteries (LIBs) are crucial for modern energy storage needs, enabling a diverse array of applications, from portable electronics to electric vehicles and grid‐scale systems. Despite significant advancements, the cathode remains a key bottleneck limiting energy density and cost efficiency. This review delves into the evolution of cathode materials, highlighting their structural and electrochemical advancements. While the development of layered oxides, spinel oxides, and polyanion oxide cathode materials has broadened the voltage range and energy density, significant challenges persist. Key challenges include electrolyte degradation, transition metal dissolution, phase instability, and structural degradation under high cycling voltage. The review emphasizes innovative strategies to mitigate these limitations, including surface coating, elemental doping, novel binders, particle size modification, prelithiation, electrolyte formulation, etc. By addressing key challenges and proposing robust solutions, this work provides a roadmap for advancing LIB cathodes, driving further innovation toward safer, more efficient, cost‐effective, and high‐energy storage solutions.

Off-grid energy solutions in cold climates face unique challenges due to extreme temperatures, high heating demands, and limited solar generation during winter months. This chapter explores the role of hybrid energy storage systems in improving energy reliability, efficiency, and sustainability for off-grid applications in such environments. A particular focus is given to a comprehensive case study of a dairy farm, where hybrid heat, power, and energy storage solutions are integrated to meet diverse energy needs. The case study presents a technical, economic, and environmental assessment comparing a fully electric-driven system with a hybrid electric-thermal storage approach. The analysis evaluates system performance in terms of energy security, cost reductions, CO₂ emissions, and overall efficiency.

Changes in energy intake and cost of transport by skipjack tuna (Katsuwonus pelamis) during northward migration in the northwestern Pacific Ocean

Abstract. The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit simulation of extracted netlist is 768 MHz under typical, and 463 MHz under worst case technology and application corner conditions, respectively. Simulated dynamic power dissipation is 0.24 uW MHz−1 at 0.9 V; static power is 38 uW in slow corner, 65 uW in typical corner and 518 uW in fast corner, respectively. The latter can be reduced by 43% in a 40-nm CMOS technology using 0.5 V reverse-backbias. These features are compared with the results from different design styles as well as with an implementation in 28-nm CMOS technology. It is interesting that in the latter case area scales as expected, but worst case performance and energy do not scale well anymore.