New CMOS integrated pulse width modulator for voltage conversion applications

This paper describes the design of a SiC pulse width modulation (PWM) signal generator in the HiTSiC® CMOS process from Raytheon Systems Limited. The high-temperature applications of the circuit include motor control in heavy equipment, deep earth drilling, dc-dc voltage converters and power inverters. The results presented in this paper are for the PWM circuit operating with an input clock frequency of 100 kHz and a supply voltage range of 12 to 15 V. The building blocks for the PWM include a current-starved delay generator, a comparator and XNOR gates. The delay is controlled by a 6-bit binary input that allows the user to dynamically tune the duty cycle. Experimental results show the circuit to have a tunable duty cycle between 16.3% and 84.3% at 400°C.

Series capacitor buck (SC Buck) converters are widely used in voltage regulator modules (VRMs), electric vehicle, photovoltaic (PV) systems, and so on, for the reason that these converters have the characteristics of high step-down ratio and large output current. However, these characteristics can be realized only when the converter operates in a limited duty-cycle range. In this article, a modified pulsewidth modulation (PWM) scheme based on the principle of ampere-second balance is proposed for the three-phase SC Buck converter to solve the problem. The ampere-second balance of series capacitors is used to balance the phase currents over the entire duty-cycle range. The operating modes, voltage gain and current sharing performance of the converter, control diagram of the proposed converter, and parameter variation analysis are given. Theoretical analysis shows that with the proposed PWM scheme, the converter will have a larger output voltage, unified linear voltage gain expression, and sensorless automatic current sharing over the full duty-cycle range. Moreover, the results show that the parameter variation has nearly influence on the current sharing effect and the excellent balanced current can be achieved under steady state and transient state using the proposed PWM scheme. Finally, a 100-W experimental prototype has been fabricated to verify the performance of the proposed PWM scheme.

The drives of power amplifiers of magnetic levitation servo spindle applied to micro EDM (Electron discharge machining) based on FPGA (Field programmable gate array) are developed. The drive module that produces the PWM (Pulse width modulation) waves that conform to the requirements of spindle power amplifiers involving three-level half bridge switch power amplifier, three-level full bridge switch power amplifier and motor power amplifier, according to input of action values from magnetic levitation servo spindle controller DSP (Digital signal processor) is designed. Multi-PWM producing algorithm by single timer with multi comparing nodes is proposed. After being applied to control system of magnetic levitation servo spindle, the drives accomplish conversion from DSP action values to PWM waves. The PWMs that drive radial coil current power amplifier have phase difference of 180°. The PWMs that drive axial coil current power amplifier have dead zone time and their wave shapes are complementary. The PWMs that drive the motor power amplifier conform to requirements of power amplifier chip LMD18200. Using FPGA to realize the drive function of spindle power amplifier makes the drive design more flexible, resource distribution of DSP more optimized, the task of algorithms running more centralized, and the drives module gets simpler and more reliable because the phase shift circuit and dead zone circuit are cancelled but the function of phase shift and dead zone is reserved.

A radiation-hardened-by-design (RHBD) voltage- controlled delay line (VCDL) for single-event mitigation in delay-locked loops (DLLs) is proposed. A modified fully differential delay cell topology is used to harden the VCDL, resulting in a dramatic reduction of the missing pulses generated by the DLL after an ion strike. By increasing the width-to-length ratios of the feedback transistors of the VCDL delay cells, this topology provides substantially reduced single-event errors while maintaining high operating frequency, wide tuning range and small area penalty.

Voltage source inverter (VSI) is one of the most common types of power converters, which is used in various industries. The energy efficiency indicators of the AVI depend not only on the IGBT or MOSFET-based transistors used in the AVI element, but also on the chosen modulation algorithm.The most commonly used in VSI is pulse width modulation (PWM) and single modulation. The advantage of PWM prior to single modulation is the ability to control the amplitude of the first harmonic of the output voltage and, accordingly, the current required both for scalar and vector control of an asynchronous electric drive.At the same time, the disadvantage of PWM is the need for a higher switching frequency of power switches, which results in higher dynamic losses. In addition, in the PWM mode, VSI at the same load parameters has a smaller amplitude of the first harmonic of the output voltage, and hence less output power.The article proposes the use the mode of overmodulation algorithm in the pulse-width modulation (PWM) mode for a three-level autonomous voltage inverter, which is relatively classical PWM with a modulation factor equal to one, justified and allows to increase the control range of the output power of the VSI, to reduce the dynamic losses in the power switches, to improve the sinusoidal output current, as well as reduce the ripple factor of the input current. Given the dependence of the energy indicators of the VSI on the modulation factor in the mode of overmodulation.In the specialized MelcoSim program from Mitsubishi, the calculation of static and dynamic losses in the power switches of an autonomous voltage inverter in the mode of overmodulation was performed. The dependences of the output power on the modulation coefficient, the dependence of the amplitude of the first harmonic of the output current on the modulation coefficient, the dependence of the coefficient of harmonic distortion of the output voltage on the modulation coefficient, the dependence of the harmonic distortion factor of the output current on the modulation coefficient, and the dependence of the losses in the power switches on the modulation coefficient.

An interleaved series resonant converter with fixed frequency pulse-width modulation (PWM) is presented to achieve load current sharing, ripple current cancelation, zero-voltage switching (ZVS) for power switches and zero-current switching (ZCS) for rectifier diodes. Two three-level DC converters with clamped diodes and flying capacitor are adopted to share load current. The voltage stress of power switches is clamped at one-half of DC bus voltage. The interleaved PWM scheme is used to control two converters in order to reduce the output current ripple and size of output capacitor. The series resonant tank in three-level PWM converter is adopted to realise ZVS turn-on for all power switches andZCS for rectifier diodes. Thus, the switching losses of active switches are reduced and the reverse recovery losses of rectifier diodes are eliminated. The fixed frequency PWM operation is adopted to regulate output voltage, so that the drawback of a wide range of switching frequency in the conventional series resonant converters is overcome. Finally, experiments based on a scale-down prototype are provided to verify the effectiveness of the proposed converter.

This paper initially presents the results of the analysis of a non linear on/off control system which is capable of generating a pulse width modulation (PWM). This technique can be used to design PWM choppers that can be dedicated to regulate fluctuating power supplies (photovoltaic, wind turbines, etc.). However, since the PWM losses mainly depend on the switching frequency, thus, the determination of an optimal frequency is required. Indeed, on the one hand, we seek to operate at high frequencies to reduce the residual noise by filtering. On the other hand, there is a limitation of the switching frequency due to the physical switching elements properties. Therefore, a compromise has to be made in order to determine an optimal switching frequency that minimizes the switching power losses. The main objective of this work is to present a technique that enables to sizing the chopper parameters based on the minimizing of the switching losses. An illustrative example of the proposed technique for sizing a PWM chopper is presented.

The power amplifier is a primary component in the control system of the magnetic suspending flywheel, which has to supply the electromagnet coil current proportional to an input voltage signal to generate the required magnetic field force. In this paper, a Pulse Width Modulated (PWM) switching power amplifier with a necessary Proportional Differential (PD) correction circuit is designed for the control system of the magnetic suspending flywheel. The experimental results shows that PWM power amplifier with PD correction features high efficiency, low signal distortion, broad bandwidth, and wide linear range and can meet the requirement for the control system of the magnetic suspending flywheel.

This paper proposes a development of Pulse-Width Modulation (PWM) switching signals based on Field Programmable Logic Array (FPGA) and Digital Signal Processor (DSP) to control multi-input interleaved DC/DC converter (MIC). The proposed PWM signals for the MIC do not only require a control of duty cycle, but also operation at different PWM frequency. In order to solve this problem, a simple programmable control scheme using a digital controller can be employed to facilitate the realization of PWM signals generation. The PWM signals are designed by using Altera Cyclone II FPGA board. The duty cycle employed to regulate output voltage is attained from the dSPACE DS1103 board using a Proportional-Integral (PI) controller. This paper also highlights design guidelines, simulation and experimental results. Experiment results show that the proposed DC converter can be driven by PWM signals, by integration of both controllers.

It is generally accepted that interleaving techniques are efficient at reducing the input/output ripples and increasing the power output of boost converters operating in critical conduction mode. This paper gives performance comparison between two famous techniques used to drive power switches; pulse width modulation (PWM) and simplified sigma delta modulation (SSDM). The control strategy of the first converter is based on a voltage mode-controlled Pulse Width Modulation (PWM) with a Proportional-Integral-Derivative (PID) controller. Pulse width modulation (PWM) is used to produce the switching pattern. But this technique causes large switching noise peaks at a multiple number of the carrier frequency. The second converter is use SSDM control loop, the output response obtained by this method is very much improved compared to the conventional PWM method of control. Simulation results are provided to illustrate the advantages of the SSDM method and controller scheme. All the advantages of interleaving, such as higher efficiency and reduced ripple for voltage/current, are also achieved.

Carrier-based sinusoidal pulse-width modulation techniques for flying capacitor modular multi-level cascaded converter

Nowadays power inverters are widely used in various applications which range from domestic to industrial facilities. The Pulse Width Modulation (PWM) techniques are extensively used for the controlling of inverter circuit in which dead time, duty cycle, and frequency are important performance parameters. In the case of controlling multiple inverters with a single controller, control signals with embedded dead-time for all the inverters may lead to poor performance for some inverters due to shoot through and controlling of multiple inverters with common duty cycle and frequency cannot fulfill the requirement. Moreover, the use of an individual controller for each inverter is not cost-effective. In this work, the PWM switching strategies are designed with Verilog Hardware Description Language (HDL) and implemented using Xilinx Spartan-6 Nexys3 FPGA with precise control of dead time, duty cycle and frequency. This FPGA based controller enables us to control any inverter designed for a specific purpose and the same inverter for different applications by configuring its frequency and duty cycle. For the present work, we have generated six PWM signals with three different dead times and duty cycles which can control three single-phase PWM inverters with specified dead time and found that FPGA implementation provide desired output with negligible distortion avoiding shoot through.

The designed switch mode power supply source (SMPS) is described. It consists of a net filter, power factor correction (PFC) circuits, pulse width modulation (PWM) controller, driver stage, PWM output stage, output transformer and voltage converter. The PFC principle is described in detail. The PWM output part was designed to deliver output power of the SMPS up to 1200 W. The calculated and the measured parameters of the output pulse transformer and the filter inductor are given. The measured values of the designed SMPS show the efficiency nearly 90% at the half and the maximum output power value.

A Flash analog-to-digital converter (ADC) architecture operating in time-domain is presented. The proposed ADC uses voltage controlled delay lines (VCDLs) and time-domain comparators instead of pre-amplifiers and voltage-domain comparators in the conventional Flash ADC. Due to the time-domain operation, the proposed Flash ADC benefits from fast switching speed of advanced CMOS process. A key property of the proposed ADC is that its linearity is not affected by the non-linearity of the VCDL, due to the identical VCDLs that are used in both the input signal and reference voltages.

This paper presents a new active capacitor voltage balancing control method for the flying capacitor multicell (FCM) converters which is fully implemented using logic-form equations. The proposed active capacitor voltage balancing control technique, measures output current and flying capacitor (FC) voltages to generate the switching states in order to produce the required output voltage level and to balance FCs’ voltages at their reference values. Output voltage of the FCM converter controlled with proposed active capacitor voltage balancing method can be modulated with any pulse width modulation (PWM) technique such as the phase-shifted-carrier PWM or level-shifted-carrier PWM. An advantage of the proposed active capacitor voltage balancing control method is its simplicity as it does not require any complex computations and tedious optimization calculations. Simulation results and experimental measurements of a three-cell four-level and four-cell five-level FCM converters are presented to verify the performance of the proposed active capacitor voltage balancing control technique.