New polynomial transform algorithm for multidimensional DCT

In this work, we present the fabrication of bulk micromachined microbolometers made of amorphous germanium-silicon-oxygen compounds (Ge/sub x/Si/sub 1-x/O/sub y/) grown by reactive sputtering of a Ge/sub 0.85/Si/sub 0.15/ target. We describe the complete procedure for fabricating thermally isolated microbolometers consisting of Ge/sub x/Si/sub 1-x/O/sub y/ sensing films deposited on sputtered silicon dioxide membranes suspended over a silicon substrate. The electrical properties of the sensitive material are set by controlling the deposition parameters of the sputtering technique. Under optimum deposition conditions, Ge/sub x/Si/sub 1-x/O/sub y/ layers with moderate electrical resistivity and thermal coefficient at room temperature as high as -4.2% /spl middot/ K/sup -1/ can be obtained. Isolated structures measured at atmospheric pressure in air have a thermal conductance of 3 /spl times/ 10/sup -6/ W /spl middot/ K/sup -1/ and a thermal capacitance of 6/spl middot/10/sup -9/ W /spl middot/ s /spl middot/ K/sup -1/, yielding a response time of 1.8 ms. Bolometers with an IR responsivity of 380 V /spl middot/ W/sup -1/ and a NEDT of 3.85 K at 100 nA bias current are obtained. The use of sputtered films allows designing a fully low-temperature fabrication process, wholly compatible with silicon integrated circuit technologies.

The surface of pulse septum magnet in HLS was specially coated with Al/sub 2/O/sub 3/ powder by plasma spraying. It was found with such magnet in the injection vacuum chamber the pressure was relatively low. To investigate the mechanics 20 sheets of coating were made (120 /spl times/ 80 /spl times/ 20 mm/sup 2/), adsorption capacity was tested. Pore constitution was studied by N/sub 2/ isotherm method. Results indicated ultimate pressure reduced obviously from 6.4 /spl times/ 10/sup -5/ Pa to 8.6 /spl times/ 10/sup -6/ Pa. Coat adsorption capacity is about 3.68 /spl times/ 10/sup -4/ Pa /spl middot/ 1/cm/sup 2/. BET surface area is 201 m/sup 2//g, Coat is porous and pore is closed at one end. XPS results indicate there are hydroxyl, carboxyl etc., on the surface, and they are most probably related with adsorption.

Recent progress in developing large area HTS-coated stainless steel tapes is reported. YBCO films have been grown on IBAD-YSZ buffered 0.1 mm-thick steel tapes using a high-rate pulsed-laser-deposition technique which allows a deposition rate up to 70 nm /spl middot/ m/sup 2//h. The coated conductors (CC) are provided with an optimized shunt layer and current contacts which reduce the generation of Joule's heat. An advanced technique for critical current I/sub c/ measurements was developed. The effects of self-field and time relaxation of current in helically wound tapes are analyzed. In long tapes of 10 m /spl times/ 4 mm, the highest I/sub c/ of 78 A at 77 K was observed. Critical currents of 67-75 A were reproducibly achieved in (8-10) m /spl times/ 4 mm coated tapes. For shorter tapes with a length of 0.2-1 m, critical currents of 317-391 A/cm width of the tape were observed. Fifteen wider CC tapes of 0.6 m /spl times/ 43 mm with I/sub c/ = 700 A have been manufactured and employed in newly developed fault current limiters with a nominal current of 3 kA. Critical current densities J/sub c/ = (1.3-2.5) MA/cm/sup 2/ at 77 K were observed in YBCO films. The CC tapes exhibit favorable behavior under axial stress and sufficiently small ac losses.

This paper presents the optimal guaranteed performance for a multiple-antenna wireless compound channel with M antennas at the transmitter and N antennas at the receiver on a Ricean fading channel with a static specular component. The channel is modeled as a compound channel with a Rayleigh component and an unknown rank-one deterministic specular component. The Rayleigh component remains constant over a block of T symbol periods, with independent realizations over each block. The rank-one deterministic component is modeled as an outer product of two unknown deterministic vectors of unit magnitude. Under this scenario, to guarantee service, it is required to maximize the worst case capacity (min-capacity). It is shown that for computing min-capacity, instead of optimizing over the joint density of T /spl middot/ M complex transmitted signals, it is sufficient to maximize over a joint density of min{T, M} real transmitted signal magnitudes. The optimal signal matrix is shown to be equal to the product of three independent matrices - a T /spl times/ T unitary matrix, a T /spl times/ M real nonnegative diagonal matrix, and an M /spl times/ M unitary matrix. A tractable lower bound on capacity is derived for this model, which is useful for computing achievable rate regions. Finally, it is shown that the average capacity (avg-capacity) computed under the assumption that the specular component is constant but random with isotropic distribution is equal to min-capacity. This means that avg-capacity, which, in general, has no practical meaning for nonergodic scenarios, has a coding theorem associated with it in this particular case.

Efficient test generation methods and design-for-testability schemes are critical to ensure the quality of multimedia cores. By investigating the potential test problems existing in these cores, This work presents a series of efficient test methods to significantly reduce the test application time for these cores while obtaining 100% fault coverage. The test development procedure is demonstrated by employing a well-known 2-D discrete cosine transform (DCT) circuit that is implemented in the typical row-column decomposition method. The 100% fault coverage is first achieved by appropriately modifying the original design, including scan design insertion and some ad hoc revisions. We then apply the recently-developed input reduction method and the broadcasting scan method to overcome the deficiency of long test application time when inserting scan design into the circuits. With these two methods, the test application time can be reduced to 6.8% of those required by the single full scan designs, while only 7.9% area overhead is needed.

The proliferation of pervasive devices has stimulated the development of applications that support ubiquitous access via multiple modalities. Since the processing capabilities of pervasive devices differ vastly, device-specific application adaptation becomes essential. We address the problem of speech application adaptation by dialog call-flow reorganisation for pervasive devices with different memory constraints. Given an atomic dialog call-flow A and device memory size m, we present optimal deterministic algorithms, RESEQUENCE and BALANCE-TREE, which minimise the number of questions in the reorganised output call-flow A/sub m/. Algorithms MASQ and MATREE produce C/sub m/, minimally distant from input call-flow A/sub m/ while accommodating the memory constraint m. These two minimisation criteria are capable of capturing various usability requirements important in dialog call-flow design. The following observation forms the cornerstone of all the algorithms in this paper: Two grammars g/sub 1/ and g/sub 2/ comprising of |g/sub 1/| and |g/sub 2/| elements respectively can be merged into a single grammar g = g/sub 1/ /spl times/ g/sub 2/ having |g/sub 1/|/spl middot/|g/sub 2/| elements for the sequential case, and g = g/sub 1/ + g/sub 2/ having |g/sub 1/|+|g/sub 2/| elements for the tree case. Device-speciific considerations lead us to introduce the concept of an <m,q>-characterisation of a call-flow, defined as the set of pairs {(m/sub i/,q/sub i/)| /spl isin/ N}, where q/sub i/ is the minimum number of questions required for memory size m/sub i/. Each call-flow has a unique, device-independent signature in its <m,q>-characterisation - a measure of its adaptability. We present SAMVAAD, a system that implements these algorithms on call-flows authored in VXML containing SRGS grammars. The system was tested on an IBM voice browser using a sample airline reservation system call-flow reorganised for memories ranging from 64 MB to 210 KB. We ran an experiment with 14 users to obtain feedback on the usability of the adapted call-flows.

In the paper “An analog 2-D DCT processor,” authors have presented a row-column method for computing 2-D discrete cosine transform (DCT). They have reported minimum peak signal-to-noise ratios (PSNR) 40.6 dB and 31.4 dB for 4-point and 8-point DCT, respectively. The main objective of this comment letter is to point out that those PSNR values are not correctly calculated. The actual minimum PSNR values are shown to be 24.7 dB and 22.7 dB for 4-point and 8-point DCT, respectively. Similarly, maximum PSNR values are corrected in this letter.

Discrete cosine transform(DCT) is one of the most powerful tools in image processing. In this paper, we show that each basis of the two dimensional discrete cosine transform (2D-DCT) is an ldquoeigenvectorrdquo of the frequency matrix which is used to obtain basis images of a two dimensional frequency transform (2D-FRT). We also connect the FRT and cosine transform in 1D continuous model. Then, the frequency cosine transform (FCT), is proposed based on the FRT and the DCT. The partial frequency cosine transform (PFCT) is given and discussed in details. It is shown that the FCT can be regarded as a special case of FRT or DCT and it is as sophisticated as the FRT and as fast as the DCT.

In this work, a mechanism contributing to the blocking artifacts of standard block based transform coding schemes is stated and a simple solution is proposed for reducing its effect. The proposed solution can be easily incorporated into the encoding algorithms of existing two dimensional (2-D) discrete cosine transform (DCT) based image and video coding standards (JPEG, MPEG-1 and 2, H-261, H-263) without the need for a modification in their bitstream syntax.

In this paper, we proposed a fingerprint matching using the two dimensional discrete cosine transform features. In this paper we crop input images from the size 480×640 pixels into 128×128 pixels, and then divided the image into 64 sub-images, earth sub_images have the size 16×16 pixels. We measure our algorithm performs by the correlation value of the 2D discrete cosine transform (DCT) and 2D Fourier transforms (FFT). And we used images for testing are obtained from FVC-2004 (DB-1A) and FVC - 2002 (DB2-A). From this evaluation and results, we can see that this method offers better performance when compared to other individual matching. Moreover, our method is not sensitive to rotational effect. The proposed technique is based on the availability of core point, therefore, the proposed technique introduce some errors if the core point cannot be located or improperly located. The matching is performed using the two dimensional discrete cosine transform and two dimensional Fourier transform to find the magnitude of the spectrum, spectrum phase, and the value of line angle.

This paper proposes an efficient parallel adder based design for 1-D any-length discrete Cosine transform (DCT). Using the similar idea to the Chirp-Z transform, we develop an algorithm formulating the 1-D any-length DCT as cyclic convolutions. The proposed design using this algorithm not only owns higher flexibility in the transform length, but also possesses low hardware cost by using the parallel adder implementation. Considering an example using 16-bits coefficients, the proposed design can save much gate area as compared with other designs in the longer transform length applications.

The authors first propose an index mapping such that the type-IV m-dimensional discrete cosine transform (m-D DCT-IV) is turned into a sum involving a number of (m−1)-dimensional discrete cosine transforms ((m−1)-D DCTs). Then a polynomial transform is used for implementing the sum. Based on symmetrical properties, a refined fast polynomial transform algorithm is proposed for computing the polynomial transform. Compared to the row–column m-D DCT-IV algorithm, the proposed algorithm achieves remarkable savings in arithmetic operations. More precisely, the numbers of multiplications and additions for m-dimensional DCT-IV are nearly 1/m and (2m+1)/3m times those of the row–column method, respectively.

This paper makes use of one dimensional Discrete Cosine Transform (DCT) to design an efficient palmprint based recognition system. It extracts the palmprint from the hand images which are acquired using a flat bed scanner at low resolution. It uses new techniques to correct the non-uniform brightness of the palmprint and to extract features using difference of 1D-DCT coefficients of overlapping rectangular blocks of variable size and variable orientation. Features of two palmprints are matched using Hamming distance while nearest neighbor approach is used for classification. The system has been tested on three databases, viz. IITK, CASIA and PolyU databases and is found to be better than the well known palmprint systems.

In order to compress the multiview image efficiently, we propose a new basis representation by using directional sampling.Because the multiview image has the static correlation related to the camera position, directional sampling can eliminate the correlation efficiently. We apply directional three dimensional Discrete Cosine Transform (directional 3D-DCT), directional three dimensional Discrete Wavelet Transform (directional 3D-DWT) and directional three dimensional Principal Component Analysis (directional 3D-PCA) to three dimensional data that has vertical, horizontal and view axis. In the experimental results, the method by using directional sampling showed better quality than conventional sampling, not only in the objective evaluation, but also in the subjective evaluation. Furthermore, the proposed method showed better Rate-PSNR than conventional method (disparity compensation).

A novel implementation of Two Dimensional Discrete Cosine Transform (2D-DCT) using Embedded Programmable Logic Devices (EPLDs) has been proposed in this paper. The key feature of this scheme is that it's architecture is regular, linear, pipelined and it fits into just four numbers of commercially available EPLDs. It is capable of processing images of size 512/spl times/512 pixels at rates of 25 frames per second. The chip set offers device independent design and can be used in conjunction with other processors. The algorithm implemented can be easily modified and remapped as per needs with a minimum of effort since the architecture is realized using modular Hardware Description Language (HDL). The hardware complexity and accuracy of the proposed DCT processor compare favourably with those of other known implementation techniques.