Non-intrusive testing of high-speed CML circuits

Due to the low mobility and the abundance of trap states in organic field-effect transistors (OFETs), the operation of conventional logic circuits-based OFETs needs a large voltage swing, and suffers large switching noise and low speed. In this letter, current-mode logic (CML) circuits composed of organic source-gated transistors (OSGTs) are proposed for high-speed signaling based on existing material and process technologies. Mixed-mode simulations show that CML circuits using simple resistive loads can still be operated much faster than an ideal conventional inverter with perfect active loads and OFETs free of traps. With the same supply voltage and device parameters, CML circuits can work with a wide range of signal swings. The superior analog performance of OSGTs is also shown to fit well with the design requirements for CML circuits in terms of low power supply, high output impedance, and stability.

New BiCMOS current-mode logic (CML) circuits employing multiemitter devices are proposed. They perform logic functions in addition to conversion from CMOS to CML (or ECL). Their transient behavior was analyzed, and their delay expressions were obtained and verified using HSPICE. These expressions were used to optimize their design. Their performance s compared with other BiCMOS CML circuits with similar functionality.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents the design of a multiple-valued current-mode (MVCM) logic circuit with a low supply voltage for high-speed arithmetic systems at low power dissipation. A multiple-valued differential logic circuit (DLC) is used as a basic component to make a signal-voltage swing small yet driving capability large. The use of DLC enables high-speed operations with reduced device and interconnection counts at low power dissipation.

A 25-Gb/s half-rate clock and data recovery (CDR) IC using a current-mode logic (CML) buffer circuit with a latch load circuit for delay generation is presented. To achieve low-power operation of the CDR, the latch-load circuit for delay generation is combined with a CML buffer circuit, which provides a wide controllable delay range. This enable a reduction in the number of the CML circuits for delay generation used in the CDR IC. To confirm the validity of the proposed method, we fabricated a 25-Gb/s half-rate CDR IC with the 65-nm CMOS process. The power consumption of the proposed circuit is around half that of the conventional half-rate CDR circuit The area for the core circuits is 0.09 mm2, and the power consumption without output buffers is 96mW.

In this paper, we present a new RF built-in self test (BIST) circuit for 865–870 MHz low noise amplifiers (LNAs); The BIST and LNA circuit is designed using 0.35µm CMOS technology. The simple circuit of test that contains a RF peak detectors and two comparators brings high fault coverage. The faults simulating possible catastrophic and parametric faults are introduced. A total of twenty eight short and open faults and ten parameters variation have been introduced into the LNA, giving fault coverage of 89% for catastrophic faults and 90% for process variation.

On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy

Earlier approaches dealt with the detection of catastrophic faults based on I/sub DD/ monitoring. Consideration of the more subtle parametric faults and the ADC quantization noise, however, is essential for high-quality analog testing. The paper presents a new design method for analog test of parametric and catastrophic faults by I/sub DD/ monitoring. ADC quantization noise is systematically considered throughout the method. Results prove its effectiveness.

This paper proposes a transistor-level design of a high-speed 10-bit Serializer-Deserializer (SerDes) circuit for Aerospace applications, in a 28 nm CMOS technology. A data-rate above 10 Gbit/s has been taken as a target for the development, together with a −50 °C to 125 °C temperature range. The extreme performance requirements made necessary the realization of a full-custom design and the use of Current Mode Logic (CML) circuits. This solution brings advantages in devices where high speeds are required, overcoming standard CMOS logic capabilities. Moreover, an aerospace application involves an analysis over radiation and their effect on integrated circuits. The relatively low presence of cumulative radiation doses in this environment let them to be neglected and to focus the attention on the disturbs coming from high-energy particles hitting the substrate (Single Event Effects). These, in fact, constitute one of the main causes of failures in electronic devices for avionic systems.

The RC ladder network has been analyzed for various catastrophic fault detection using minimal number of measurements. Generally, electronic circuit testing procedure is very exhaustive and includes higher cost; the presented approach will save fault diagnosis time. It is not possible to analyze the big RC ladder network to give the good fault coverage, so the ladder network has been broken into segments of different sizes. However, if segment size is small, it will cause more area overhead compared to bigger step size in terms of the interconnections and pins on the integrated circuit. A systematic and detailed analysis for one-step, two-step, three-step, and four-step RC ladder networks has been carried out for various faults and optimal step size is proposed. It has been investigated that three measurements are optimal to localize different catastrophic faults in a RC ladder network.

Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for integrated circuits (ICs). ESD protection design for giga-Hz high-speed input/output (I/O) circuits has been one of the key challenges to implement high-speed interface circuits in CMOS technology. Conventional on-chip ESD protection circuits at the I/O pads often cause unacceptable performance degradation to high-speed I/O circuits. Therefore, ESD protection circuits must be designed with minimum negative impact to the high-speed interface circuits and to sustain high enough ESD robustness. In this paper, ESD protection design considerations for high-speed I/O circuits are addressed, and the patents related to on-chip ESD protection designs for high-speed I/O circuits are presented and discussed. Keywords: Electrostatic discharge (ESD), input/output (I/O) interface, low capacitance (low-C), power-rail ESD clamp circuit, LC resonator, LC-tank, impedance cancellation, impedance isolation, impedance matching, distributed ESD protection scheme

This paper discusses the behavior and design of CMOS current-mode logic (CML) circuits. The advantages of using the CML topology over static CMOS for high-speed digital signals are discussed. Biasing and dynamic behavior of CML circuits are discussed and a design method for optimizing the bandwidth and speed is presented.

An analog circuit testing scheme is presented. The testing technique is a sinusoidal fault signature characterization, involving the measurement of DC offset, amplitude, frequency and phase shift, and the realization of two crossing level voltages. The testing system is an extension of the IEEE 1149.4 standard through the modification of an analog boundary module, affording functionalities for both on-chip testing capability, and accessibility to internal components for off-chip testing. A demonstrating circuit-under-test, a 4th-order Gm-C low-pass filter, and the proposed analog testing scheme are implemented in a physical level using 0.18-µm CMOS technology, and simulated using Hspice. Both catastrophic and parametric faults are potentially detectable at the minimum parameter variation of 0.5%. The fault coverage associated with CMOS transconductance operational amplifiers and capacitors are at 94.16% and 100%, respectively. This work offers the enhancement of standardizing test approach, which reduces the complexity of testing circuit and provides non-intrusive analog circuit testing.

A new type of quaternary D flip-flop based on multiple-valued current-mode is presented for high-speed sequential circuit in VLSI systems. It employs master-slave mode and dynamic multiple-valued source-coupled logic. A distinguishable multiple-valued interval, fast switch speed and compact structure are obtained by combining source-coupled logic with differential-pair circuit. The performance evaluation is carried out with HSPICE using 0.18μm CMOS process. A performance comparison with those issued in some references is conducted. The delay in our design is about 74% reduced by comparison with the corresponding binary implementation. The circuitry proposed is simplicity, regularity, and modularity, so well suited for VLSI implementation. Quaternary logic seems to be a potential and feasible method of high-performance VLSI systems.

This paper provides evidence that, as a result of constant-field scaling, the peak fT (approx. 0.3 mA/mum), peak fMAX (approx. 0.2 mA/mum), and optimum noise figure NFMIN (approx. 0.15 mA/mum) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers

Simultaneous Switching Noise (SSN) is increasing with higher I/O data rate, resulting into more challenges in regulating supply voltage noise. SSN increases jitter in high-speed interface circuit and limits the performance of I/O. In order to reduce SSN effect to supply voltage droop, Power Distribution Network (PDN) has to be designed optimally. PDN design goal is to reduce the power supply noise going into I/O circuit. Engineering efforts are focused on packaging and board routing in order to control the impedance profile and supply voltage droop within the design specification. This paper discusses the next level of investigation, quantifying the effect of supply noise to the I/O transistor level circuit performance, specifically on Universal Serial Bus (USB) transmitter circuit. Output of the USB's transmitted signal is shown in eye diagram with the existence of supply noise throughout PDN. Results show that the USB transmitter circuit can sustain with higher supply noise drop than the targeted PDN design.