Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach

With the development of the nuclear technology, the instrumentation and control (I&C) systems have evolved from the analog systems to the current state-of-the-art digital systems. It has been reported that China has recently developed the digital systems based on Field Programmable Gate Array (FPGA) in CAP1400 nuclear power plant. And the lack of methods in the verification and validation work of the FPGA systems has become an important issue. This thesis describes the basic principles of FPGA, and the development process of FPGA. And then, the thesis proposes an effective improved method—formal verification, describing three methods of formal verification in detail, namely theorem proof, model checking, and equivalence proof. Describing the FPGA verification methodology and pointing out the shortcomings of traditional simulation, comparing the formal verification and traditional simulation verification in terms of complexity, timing, and applications. We also discussed the importance of formal verification method in FPGA. We selected the temperature and power control chip based on FPGA as an example, using System Verilog Assertions (SVA) method of model checking, and verifying the SRAM controller module and the internal calculation module. Through the analysis of the results, this paper proved the feasibility of formal verification methods in the instrumentation and control system of nuclear power plants, and provided some references of verification work for other system chips in instrumentation and control of nuclear power plant in the future work. The thesis showed that verification engineers can use the formal verification method based on SVA to verify the robustness of the system quickly and accurately. This method improves the controllability and observability which are the main drawbacks of the traditional simulation verification. It also avoids several issues in the debug process of traditional simulation verification, improving the accuracy and completeness of the chip verification.

During the last decades, artificial intelligence (AI) touched many domains of software engineering. One of them is formal verification (FV), where learning methods could improve the performance of several formal verification approaches. Model checking (MC) is one of the FV techniques used to verify systems. In this article, we investigate the direction of the link between MC and one of AI techniques. We survey several related works about how learning can improve MC in its functionalities. Furthermore, we give an overview of some adapted approaches of ML in MC.

The next few years will see distributed real-time computer systems playing an important role in control systems of high-dependability applications, such as rail transportation. In these applications a failure in the temporal domain can be as critical as a failure in the value domain. In rail transportation, train control system has become more complex and the methods to ensure its correctness of have been considered outmoded. The safety of train control system is becoming increasingly important as computers pervade them on which human life depends and the failure to meet time deadline can have serious or even fatal consequences. This paper proposes a formal modeling and verification approach for real-time system. In the proposed method the real-time system is modeled by timed automata network (TAN) and verified by model checking which explores the state space to determine whether the system satisfies a given specification. The case study of ATP (automatic train protection) shows how the method can assist in designing more efficient and reliable real-time systems. Firstly, automatic train protection (ATP) system and timed automata network (TAN) model is proposed; secondly, the state transitions and multi-tasks ATP onboard model was modeled with TAN model, and then the time sequences of each task are expressed in UML sequence diagrams. Finally, the timing characteristics was verified to meet the requirement by UPPAAL model checker. A major conclusion of the survey is that formal methods, while still immature in some respects, can be used successfully to model and verify real-time systems.

SummaryToday, service composition is emerging paradigm on the communication networks such as cloud environments, internet of things, wireless sensor network, and software‐defined network. The goal of service composition method is to provide the interactions between user requirements and smart objects of intelligent communication systems. There have been many efforts to use formal verification and behavioral modeling methods to evaluate the service composition mechanisms. Up to now, there is not a comprehensive analysis research on this topic. Therefore, this paper focuses on several formal verification approaches that are performed to confirm the service composition correctness in communication networks. The objective of this paper is to comprehensively categorize and examine current research techniques on formal verification of the service composition. This research analysis provides an overview of recent service composition approaches according to structural and functional properties. Comparison results show that most of the verification approaches in explanation of the service composition correctness are semantic‐aware approach with 43%. The most used verification method for the service composition is model checking with 69%. The process algebra is used 29%, and some theorem proving methods are applied in 9% of the investigated mechanism. Moreover, most widely used modeling tools are NuSMV (22%), SPIN (17%), CPN (12%), UPPAAL (12%), Event‐B (10%), and PAT (5%).

Summary form only given. Modern circuits contain up to several hundred million transistors and this number grows exponentially over time. Thus, the state-of-the-art design flows have to be improved continuously. In the meantime ensuring correctness becomes a major bottleneck. Up to 80% of the overall design costs are due to verification and even more problems are foreseeable - shrinking feature sizes lead to large process variations, increased susceptibility to radiation, etc. As a result even a correct design may contain faulty components. Thus, robustness is required, i.e. correct operation in presence of faults. Formal verification techniques have gained large attention, since they allow proving the correctness of a circuit and thereby ensure 100% functional correctness. Moreover, the underlying techniques can also be used to prove robustness of a design. Besides being more reliable, formal verification approaches have also shown to be more cost effective in many cases, since test bench creation - usually a very time consuming and error prone task - becomes superfluous. Therefore these techniques allow unveiling faulty behaviour automatically. Proving robustness in the sense of fault tolerance is important. As in any implementation step, faults may tamper the behaviour. In particular, fault tolerance may hide flaws during the standard verification step. Therefore instead of relying on the design's architectural precautions against faults, the implementation has to be proven to be fault tolerant. In this tutorial, after a brief motivation of the overall topic and definition of the problem domain, the alternative verification approaches are explained. Next, the application of the underlying formal techniques for robustness checking is considered. The standard approaches for verification are simulation, emulation and formal methods. Details are discussed related to formal verification, symbolic simulation and assertion based verification. The verification scenarios for equivalence checking (EC) and property checking (PC) are presented and the underlying proof techniques are explained. Robustness checking then also builds on the underlying formal methods. This allows analyzing the robustness of a design fully automatically. Practical scenarios covered by this model for robustness of a circuit are discussed. The model not only yields a measure for the robustness of a circuit but also shows critical parts of the implementation that should be reengineered. In comparison alternative approaches, e.g. using statistical measures, are outlined. Further references are given for all topics are given (see below). Directions for future work and research challenges are discussed.

Preface: Special issue on software verification and testing

This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader System Verilog language, demonstrating the ways that assertions can interact with other System Verilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012. System Verilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.

The verification of real-time codes implemented in embedded systems is a very important problem, as many of these systems, such as autopilot systems and medical devices, are safety critical and need guarantees of their proper operations (Edwards et al. in Proc IEEE 85(3):366–390, 1997, [1]). These embedded systems are interacting with the physical world, and thus continuous variables, such as time clocks, have to be taken into consideration. Hence, modeling such a system as a hybrid system becomes a natural choice. A typical question is whether certain properties, such as safety (e.g., bad things never happen), liveness (e.g., good things eventually happen), fairness (e.g., all nodes get a chance to transmit), and other properties, hold true or not for a given hybrid system model. Such problems are commonly known as formal verification problems. In this chapter, we will focus on the model checking approach in the formal verification literature since model checking can be fully automated and has been gaining a lot of attention from both academia and industry. Other approaches, such as deductive approaches, will be briefly mentioned at the end of this chapter.

Deep brain stimulation (DBS) is a widely accepted treatment for the Parkinson's disease (PD). Traditionally, it is done in an open-loop manner, where stimulation is always ON, irrespective of the patient needs. As a consequence, patients can feel some side effects due to the continuous high-frequency stimulation. Closed-loop DBS can address this problem as it allows adjusting stimulation according to the patient need. The selection of open- or closed-loop DBS and an optimal algorithm for closed-loop DBS are some of the main challenges in DBS controller design, and typically the decision is made through sampling based simulations. In this letter, we used model checking, a formal verification technique used to exhaustively explore the complete state space of a system, for analyzing DBS controllers. We analyze the timed automata of the open-loop and closed-loop DBS controllers in response to the basal ganglia (BG) model. Furthermore, we present a formal verification approach for the closed-loop DBS controllers using timed computation tree logic (TCTL) properties, that is, safety, liveness (the property that under certain conditions, some event will eventually occur), and deadlock freeness. We show that the closed-loop DBS significantly outperforms existing open-loop DBS controllers in terms of energy efficiency. Moreover, we formally analyze the closed-loop DBS for energy efficiency and time behavior with two algorithms, the constant update algorithm and the error prediction update algorithm. Our results demonstrate that the closed-loop DBS running the error prediction update algorithm is efficient in terms of time and energy as compared to the constant update algorithm.

Concurrent Action-Oriented Specifications (CAOS) model the be- havior of a synchronous hardware circuit as asynchronous guarded actions at an abstraction level higher than the Register Transfer Level (RTL). Previous approaches always considered the compilation of CAOS, which includes a transformation of the under-lying model of computation and the scheduling of guarded actions per clock cycle, as a tightly integrated step. In this paper, we present a new compilation procedure, which separates these two tasks and translates CAOS models to synchronous guarded actions with an explicit interface to a scheduler. This separation of con- cerns has many advantages, including better analyses and integration of custom schedulers. Our method also generates assertions that each scheduler must obey that can be fulfilled by algorithms for scheduler synthesis like those developed in supervisory control. We present our translation procedure in detail and illustrate it by various examples. We also show that our method simplifies for- mal verification of hardware synthesized from CAOS specifications over previously known formal verification approaches.

In this paper, we present a case study of formal verification of analog and mixed signal designs using SPICE circuit simulation traces. We consider verifying safety properties of Full Wave Rectifier (FWR) using SPICE circuit simulation traces. We follow the formal verification approach of where authors have used the SPICE circuit simulation traces for doing the formal analysis of the Analog and Mixed Signal circuits. We have used the Checkmate tool from CMU, which is a public domain formal verification tool for hybrid systems. Checkmate is built on the top of the Simulink/Stateflow Framework (SSF) from MATLAB from Math Works. Due to restriction imposed by Checkmate it necessitates to make the changes in the Checkmate implementation to implement the complex and non-linear systems. FWR has been implemented by using Checkmate custom blocks and Simulink blocks from MATLAB. The FWR model has been implemented in LTSPICE. The formal verification has been done for both the implementation i.e. Simulink implementation as well as LTSPICE implementation. We are able to efficiently verify the safety properties of the full wave rectifier using simulation traces from Simulink model and LTSPICE simulation.

System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on their hardware designs. However, the ambiguity of design specifications specified by different protocol standards in general and JEDEC memory protocol standards in specific imposes numerous difficulties on designers and verification engineers when translating design specifications into SVA. This motivated us to find a simple way to capture design specifications from JEDEC standard and automatically generate SVA that can be used as checkers for DDR memory protocols. In this paper, we propose a new method to capture design specifications using a timing diagram tool that documents the captured design specifications in a Timing Diagram Mark up Language (TDML) based format and generate SVA from the TDML document. The viability and the potential of our work are demonstrated with an Industrial case study using JEDEC LPDDR3 Memory Protocol Standard.

Formal modeling and verification has been under consid-erable attraction of researchers these days. Using formal methods one can find bugs and hidden errors in different systems, codes and protocols. As formal models can detect worst case scenarios which are not possible in computer simulations and other testing techniques, they are often employed by researchers to detect flaws in security protocols. A lot of hidden errors have been detected in encryption techniques and secure routing protocols by analyzing them using formal modeling and verification. Although many tools have been developed to perform formal verification; but SPIN and UP-PAAL are most frequently used by researchers to demonstrate some previously unreported weaknesses. This paper analyzes these two model checkers in terms of learning time, ease of use and their features of modeling and verification. We later annotate our findings by applying these tools against a wire-less sensor network routing protocol. We claim that our paper can help future researchers to decide which formal modeling tool is best in a particular scenario thus saving a lot of time in decision making.

Several firms are defining their Business Processes (BPs) using the standard Business Process Model and Notation (BPMN). BPs modelled with BPMN are maintained and used by different workers within a company, thus the correctness of critical BPs should be validated and verified. In this work we present how Model Checking verification technique for software has been integrated within a Formal Compositional Verification Approach (FVCA) and Timed Automata (TA) to allow the automatic verification of critical BPs modelled with BPMN. The use of our FVCA support business analysts and designers in the formal specification of BP-task model with TA. The application of the FVCA is aimed at guaranteeing the correctness of the BP-task model with respect to initial properties specification derived from business rules. In order to show a practical use of our proposal and Uppaal tool, one instance of an enterprise-project related to Customer Relationship Management business is discussed.

Purpose The purpose of this paper is to present a formal verification method to prove the correctness of social customer relationship management (CRM)-based service composition approach. The correctness of the proposed approach is analyzed to evaluate the customer behavioral interactions for discovering, selecting and composing social CRM-based services. In addition, a Kripke structure-based verification method is presented for verifying the behavioral models of the proposed approach. Design/methodology/approach Evaluating the customer behavioral interactions using the social CRM-based service composition approach is an important issue. In addition, formal verification has an important role in assessing the social CRM-based service composition. However, model checking can be efficient as a verification method to evaluate the functional properties of the social CRM-based service composition approach. Findings The results of model checking satisfied the logical problems in the proposed behavior model analysis. In the statistical testing, the proposed URM mechanism supported the four knowledge creation process conditions. It was also shown that the percentage of state reachability in the URM with KCP conditions is higher than the URM mechanism without supporting KCP conditions. Originality/value The comparison of time and memory consumption of the model checking method shows that the social CRM-based service composition approach covers knowledge process features, which makes it an efficient method.