Novel Architecture for Logic Test Using Single Cycle Access Structure

A double Hamming distance‐based 2D reordering method is proposed for a test set with don't care bits ( X s) to reduce scan‐in power and compress test patterns. In this method, the rows and columns in the test set are reordered sequentially so that similar rows or columns are aggregated together. Being different from other reordering‐based methods, the authors' method reorders every two rows or columns with more identical bits closer in the whole reordering process, where more X s are clustered. Each X is then replaced with 0 or 1 using minimum transition filling scheme to minimise '1‐0' and '0‐1' logical state transitions. A small number of the logic state transitions cause low switching activity, which not only reduces scan‐in power consumption but also facilitates code‐based test pattern compression. Experimental results show that their proposed method achieves peak and average power reductions of 18.01 and 12.97% compared to the state‐of‐the‐art method, respectively. Furthermore, the compression ratio of alternating shifted frequency directed run‐length coding is improved to 73.76% in average utilising their proposed method.

The benefits of the continued progress in integrated circuit manufacturing have been numerous, most notably in the explosion of computing power in devices ranging from cell phones to cars. Key to this success has been strategies to identify, manage, and mitigate yield loss. One such strategy is the use of test structures to identify sources of yield loss early in the development of a new manufacturing process. However, the aggressive scaling of feature dimensions, the integration of new materials, and the increase in structural complexity in modern technologies has challenged the capabilities of conventional test structures. To help address these challenges, a new logic test chip, called the Carnegie Mellon Logic Characterization Vehicle (CM-LCV), has been developed. The CM-LCV utilizes a two- dimensional array of functional unit blocks (FUBs) that each implement an innovative functionality. Properties including fault coverage, logical and physical design features, and fault distinguishability are shown to be composable within the FUB array; that is, they exist regardless of the size and composition of the FUB array. A synthesis ow that leverages this composability to adapt the FUB array to a wide range of test chip design requirements is presented. The connection between the innovative FUB functionality and orthogonal Latin squares is identified and used to analyze the universe of possible FUB functions. Two additional variants to the FUB array are also developed: heterogenous FUB arrays utilize multiple FUB functions to improve the synthesis ow performance, while pipelined FUB arrays incorporate sequential circuit elements (e.g., ip- ops and latches) that are absent from the original combinational FUB array. In addition to the design of the CM-LCV, methods for testing it are presented. Techniques to create minimal sets of test patterns that exhaustively exercise each FUB within the FUB array are developed. Additional constraints are described for the heterogenous and pipelined FUB arrays that allow these techniques to be applied for both variant FUB arrays. Furthermore, a simple built-in self test (BIST) scheme is described and applied to a reference design, resulting in a 88.0% reduction in the number of test cycles required without loss in fault coverage. A hierarchical FUB array diagnosis methodology (HFAD) is also presented for the CM- LCV that leverages its unique properties to improve performance for multiple defects. Experiments demonstrate that this HFAD methodology is capable of perfect accuracy in 93.1% of simulations with two injected faults, an improvement on the state-of-the-art commercial diagnosis. Additionally, silicon fail data was collected from a CM-LCV manufactured using a 14nm process by an industry partner. A comparison of the diagnosis results for the 1,375 fail logs examined shows that the HFAD methodology discovers additional defects during multiple defect diagnosis that the commercial tool misses for 40 of the diagnosed fail logs. Examination of these cases shows that the additional defects found by the HFAD methodology can result in improved diagnosis confidence and more precise descriptions of the defect behavior(s). The contributions of this dissertation can thus be summarized as the description of the design, test, and diagnosis of a new logic test chip for use in yield learning during process development. This CM-LCV can be adapted to meet a wide range of test chip requirements, can be efficiently and rigorously tested, and exhibits properties that can be used to improve diagnosis outcomes. All of these claims are validated through both simulated experiments and silicon data.

The oscillation test methodology is presented for active RC filters. The authors develop general guidelines for the design of the oscillation-based test structures and describe in more detail test transformations of filter configurations which are most frequently used in practice. Frequency measurements performed on some implemented test structures and fault detection experimental results are included. The oscillation-based test described in the paper is primarily intended for field testing. In some cases, it can also be used as a functional go no-go test in production. The presented test structures can also be employed for stimulus generation in a built-in self-test.

Existing built-in self-test (BIST) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. In this paper, we propose an entirely new approach to generate test patterns. The method is based on adders widely available in data-path architectures used in digital signal processing circuits and general purpose processors. The resultant test patterns, generated by continuously accumulating a constant value, provide a complete state coverage on subspaces of contiguous bits. This new test generation scheme, along with the recently introduced accumulator-based compaction scheme (Rajski and Tyszer, 1993) facilitates a BIST strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and no area overhead.

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. In this paper, we propose a novel method for implementing test pattern generators based on adders widely available in data-path architectures and digital signal processing circuits. Test patterns are generated by continuously accumulating a constant value and their quality is evaluated in terms of the pseudo-exhaustive state coverage on subspaces of contiguous bits. This new test generation scheme, along with the recently introduced accumulator-based compaction scheme facilitates a BIST strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and area overhead.

Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional Built-in Self Test (BIST) generators rise unnaturally the power consumption during testing, boosting the need to add low-power solutions to the arsenal of BIST pattern generators. In this paper, the utilization of gray code generators is proposed as a low-power BIST solution. More precisely, we show how the time required to apply a given test pattern can be decreased, by switching between different gray sequences during the application of the test set. Experimental results indicate that the time required to embed the test set within a low-power sequence is reduced to almost 50%, compared to a previously proposed solution.

Design for low power testing is primary concern in modern VLSI circuits. In this paper a novel test pattern generator (TPG) is proposed which is more suitable for built in self test (BIST) architecture, used for testing of VLSI circuits. The objective of the BIST is to reduce power consumption during testing of VLSI circuits. In CMOS devices 80% of power consumption is due to switching activity occurred during operation. The proposed TPG is based on read only memory (ROM) which is carefully designed to store the test vectors with minimum area over the conventional ROM. This reduces the number of CMOS transistors significantly when compared to that of LFSR/counter TPG. The proposed TPG is more suitable for deterministic pattern testing and the fault coverage is improved over the LFSR. Low power reordered test patterns also can also be stored in the same order to reduce the test power in circuit under test (CUT). The TPG is designed and implemented for benchmark circuits ISCAS 85 and 89. Experimental results shows that a considerable reduction in number of CMOS devices and test power is achieved over the LFSR-TPG

Most previous DFT-based techniques for low-capture-power broadside testing can only reduce test power in one of the two capture cycles, launch cycle and capture cycle. Even if some methods can reduce both of them, they may make some testable faults in standard broadside testing untestable. In this paper, a new test application scheme called partial launch-on-capture (PLOC) is proposed to solve the two problems. It allows only a part of scan flip-flops to be active in the launch cycle and capture cycle. In order to guarantee that all testable faults in the standard broadside testing can be detected in the new test scheme, extra efforts are required to check the overlapping part. In addition, calculation of the overlapping part is different from previous techniques for the stuck-at fault testing because broadside testing requires two consecutive capture cycles. Therefore, a new scan flip-flop partition algorithm is proposed to minimize the overlapping part. Sufficient experimental results are presented to demonstrate the efficiency of the proposed method.

Excessive power dissipation caused by large amount of switching activities has been a major issue in scan-based testing. For large designs, the excessive switching activities during launch cycle can cause severe power droop, which cannot be recovered before capture cycle, rendering the at-speed scan testing more susceptible to the power droop. In this paper, we present a methodology to avoid power droop during scan capture without compromising at-speed test coverage. It is based on the use of a low area overhead hardware controller to control the clock gates. The methodology is ATPG (Automatic Test Pattern Generation)-independent, hence pattern generation time is not affected and pattern manipulation is not required. The effectiveness of this technique is demonstrated on several industrial designs.

In this research, a BIST (built in self test) architecture for testing crosstalk effects in highly dense Through Silicon Via (TSV) placed in structured array form, in 3DICs (Three Dimensional integrated circuits), designed and simulated using the Xilinx ISE tool and the VHDL language. A novel methodology is proposed, and simulated, to observe the test responses of the victim TSVs in the chosen group simultaneously. Boundary-scan cell structures are modified, created for the purpose of operating in different modes such as shift, update and capture in either conventional serial shift mode as well as in proposed parallel broadcasting mode. Output Response Analyzers (ORA), or signature analyzers that have been simulation-verified. In this study, we suggested a novel encoder-based signature generator to locate faulty TSVs in the parallel-observed TSVs. This paper discusses the whole BIST architecture, the BIST controller built on an algorithmic state machine, the design of TPG (Test Pattern Generator), and the faulty TSV signature generator. Comparing the BIST architecture, to serial shift based interconnect tests done by IEEE 1149.1 (JTAG) such as EXTEST and IEEE 1838 standards, the test’s time complexity of BIST is relatively very low. The entire TSV array test is completed in just 32 clock cycles. The design is adaptable and can be used to broadcast test patterns to a group or to transmit test patterns serially using IEEE 1838 or 1149.1.

With the increasing number of embedded memories in the modern system-on-chips (SOCs), the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective technique for memory testing. However, BIST has a negative impact on physical design (e.g., area and routing). Moreover, the grouping and placement of memory BIST controllers also greatly influences the test application time. In this paper, we propose an integer linear programming (ILP) approach to optimize the memory BIST design with both physical design (grouping and placement of memory BIST controllers) and test application time considered. Experimental results consistently show that our approach works well in practice.

This paper presents a built-in self-test (BIST) design of a high-speed C-testable divider. The divider can be fully tested using 72 test patterns irrespective of the circuit size (C-testability). Its test patterns, expected outputs, and control signals can be represented by sets of labels using a graph labeling technique. Due to the simplicity of the repetitive label sets, test patterns can be easily generated inside chips and responses to test patterns need not to be stored. Thus, use of expensive test equipment is not necessary. Results show that, for the BIST design of a 64-bit C-testable divider, its hardware overhead is less than 5%.

The development of new testing techniques to prolong the life of semiconductors is seen as an important issue in integrated circuit (IC) design as new fabricated devices in the manufacture of semiconductors keep increasing in complexity and performance. Any excessive power use demonstrated in the testing may lead to yield loss, failure due to IR drop, thermal reliability issues, and overdesign. This review gives an outset exploration of the field of power-aware Design-for-Testability (DfT) methods and practices that are used to reduce the power consumption of designs under test (both dynamic as well as static power) as the test coverage of the design remains high. Important areas are low-power scan architectures, power savings via shift, scan chain reordering, compressed test patterns and power-limited automatic test pattern generation (ATPG). Emerging developments that are also discussed by the paper include 3D IC-aware DfT, AI-based test generation, and security-integrated low-power testing. The discussed strategies are assessed by their contribution to green chip production, thermal control and cost-effectiveness in modern System-on-Chip (SoC) designs. Additionally, another challenging issue under critical review is the power-thermal correlation, the increasing volume of test data, and test access overheads. The research opportunities ahead incorporate the concept of machine learning, real-time monitoring of power, context-sensitive test scheduling so that scalable, secure, and energy-aware semiconductor testing systems can be supported.

The objective involves in construction of a Logical Built in Self Test using adaptive Multiple Input Signature Register designs that is mainly used for testing of the Integrated Circuits. One of the major issues is that, the complications in integrated circuit testing have been increased due to the emerging trends in the field of Very Large Scale Integration. This problem could be solved by increasing the usage of test equipment named Logical Built in Self Test shortly called as LBIST which works much well than any other test equipments. The logical BIST also has the advantage of performing a test that is in-built to the chip by means of an extra element that is present interior to the design. Test patterns for the operation are generated always by an inbuilt testing circuit as mentioned earlier. The output responses are determined with the help of a Multiple Input Signature Register, which is the most widely as the design is completely opposite to that of a Linear Feedback Shift Register design. The testing methodology is always invoked by a MISR by means of compressing multiple sequences of input bits as a single package named as signature of the design. The fault performance during a chip testing can be improved by means of a reconstructable Linear Feedback Shift Register which functions both to generate test patterns as well as to compress the responses required for logical Built in Self Testing. The QUCS simulator and SPICE tool is used to perform compilation of fast Multiple Input Signature Register design. Four structural representations namely Basic, Combined, Programmable and Advanced MISR are implemented and simulated using QUCS simulator and SPICE tool in 22nm technology. The output waveforms of the adaptive designs are obtained for different temperature variations ranging from 27°C to 107°C.