Novel interposer scheme for 3D integration

Thin glass provides attractive solutions for emerging high frequency applications and particularly those related to the rollout of 5G. The electrical and physical properties of glass enable low RF loss, the ability to adjust thermal expansion properties, and low roughness with excellent flatness to achieve fine L/S and smaller form factors. The scalability of glass also provides opportunities to establish cost-effective solutions. There have been a number of research articles published over the past several years showing the advantages that glass based solutions can bring to packaging and systems integration including RF front ends, interposers, MEMs devices, and integrated photonics. [1-10]. RF applications of glass in particular are gaining interest for use as a substrate for filters, switches, true time delay modules, and millimeter antenna arrays. The advantages include low insertion loss relative to Si-based solutions and higher integration density compared with laminates and ceramics. Furthermore, numerous articles have shown the ability of glass to provide reliable solutions. These tests have included, HAST, thermal shock and drop tests [e.g. 5, 8]. The biggest challenge to adopting glass-based solutions has been the existence of gaps in the supply chain, caused primarily by the difficulty in handling large, thin glass substrates using standard automation and processing equipment. A new thin glass handling approach, Viaffirm TM, has been recently developed. [12,13] The approach utilizes a thin inorganic adhesion layer to temporarily bond a thin glass wafer to a silicon or glass handle wafer (Si handle wafer is the primary approach). The thin glass substrate, which may contain through-glass vias (TGVs), is then processed through downstream steps such as via fill, CMP, RDL/passive deposition, lithography and bumping. The bond is stable (remains temporary and without outgassing) to over 400 °C. Utilizing a Si handle wafer allows the thin glass to be processed leveraging existing equipment and process flows, with only a mechanical de-bond to yield finished substrates. In previous publications, the basic process has been described. Here, we will show advancements and application of this technology, with and without TGV, to seamlessly interface with the supply chain to fabricate next generation thin glass solutions for applications including photonic substrates, RF filters and antennas. The process is available for multiple glass types including alumino-borosilicate glasses with coefficient of thermal expansion that matches silicon, as well as ultra-low loss materials like fused silica (FS). Leveraging the precision bond Viaffirm allows you to fabricate FS wafers down to 100 um thick. The approach is enabling low loss solutions in electronically steerable antenna (ESA), radar arrays, MEMS, sensors and packaging substrates. A particularly attractive use for glass is in 5G applications due to its material properties, especially at high frequencies including mm-Wave applications. First, it is stable with respect to environmental changes (e.g. temperature and humidity). Also, glass is an isotropic material by nature, which means its properties are stable in all 3 axes. This can be very important in applications such as phased array antennas where you might have an 8x8 array of patch antennas, and require them all to perform predictably and with minimal variation to achieve desired results, such as in beam steering. Recent work was done to fabricate a multi-layer glass based Electronically Steerable Array (ESA) antenna with a design transmit signal of approximately 29.5 GHz. Additional architectural enhancements in this novel approach enable a dramatic reduction in the number of controllable elements in the array and therefore reduce the number of MMICs needed for antenna steering, resulting in a design with reduced size, weight, power and cost relative to more conventional approaches. [14] The approach utilized a multi-layer glass-based feed network to control 8x8 patch arrays. Analysis shows that by utilizing glass instead of PCB solutions, dramatic reduction in electrical loss are realized. By leveraging Viaffirm technology, thin glass solutions are available to address these and other mmWave applications important in 5G and beyond.

The most singular focus of the electronics industry during the last 50 years has been to miniaturize ICs by miniaturization of transistors and on-chip interconnections. Two major problems are foreseen with this approach; (1) electrical leakage and (2) the lack of improved electrical performance beyond 16nm. As a result, the industry is transitioning from the current SOC-based approach to a through-silicon-via (TSV) based 3D IC-stacked approach. However, a major challenge remains; these 3D ICs need to be interconnected to other ICs with a much higher number of I/Os than are available with current ceramic or organic interposers. While silicon interposers currently in development can provide these high I/Os, they cannot do so at low enough cost. In this extended abstract, 3D Glass Solutions, a division of Life BioScience, Inc., presents our efforts in glass interposer microfabrication. Glass interposers possess many advantages over silicon interposers including: cost, production time, and scale. 3D Glass Solution’s APEX™ Glass ceramic is a photo-sensitive material used to create high density arrays of through glass vias (TGVs) using three simple processing steps: exposure, baking, and etching. To date, we have been successful in producing large arrays of 12 micron diameter TGVs, with 14 micron center-to-center pitch, in 125 micron thick APEX™ Glass ceramic. This extended abstract covers (1) on our efforts producing high aspect ratio TGVs in ultra thin (75–250 micron) APEX™ Glass ceramic wafers, (2) maximum TGV aspect ratios, and (3) TGV fidelity and limits of manufacturing.

In this work, we report on in-substrate passive components using a high performance glass interposer and through glass via (TGV) technology and a multi-layer superlattice conductor architecture. Minimal RF loss is achieved using low dielectric loss glass substrates and superlattice conductors featuring skin effect suppression. Half mode substrate integrated waveguide (HMSIW) resonators and two-pole bandpass filters, embedded inside a glass interposer substrate, are used as test vehicles for the demonstration of insertion loss improvement in K-band. The utilized conductor is made of 20 layers of Cu/NiFe with each pair of 360 nm/30 nm, respectively, where NiFe layers with negative permeability in frequency range of interest are used for eddy current cancelling and improving the conductor loss. Control devices using the same glass substrate and conductor made of pure copper are fabricated for comparison purposes. The glass interposer substrate (SGW3, Corning Incorporated) has a thickness of 0.13 mm and the TGV's with a diameter of 0.08 mm. Up to 0.3 dB reduction in the insertion loss is achieved by using the proposed superlattice approach on glass substrates.

Glass interposers have gained increased attention and interest in microelectronics industry since 2010. This is because glass has a tailorable coefficient of thermal expansion (CTE), high mechanical rigidity, availability in large and thin panel form, low processing cost, smooth surface for fine line and space fabrication, and superior electrical properties. While thin glass panels offer such a plethora of benefits, there are several processing and reliability challenges that glass imposes. As a brittle material, glass has low fracture toughness and is prone to cracking.

The demands for increased data transmission rates and bandwidth as well as reduced signal loss are increasing while package size is getting bigger. To accommodate increasing package size and manage high frequency loss and warpage management, Glass substrates in advanced packaging are gaining momentum for heterogeneous integration of advanced semiconductor packaging. Based on Yole report in 2020, a 2.5-3 fold increase from 2019 to 2025 for the glass substrates is predicted. Glass core and Glass interposer could become a leading processing technology in advanced Panel Level Packaging (PLP). Cost effectiveness and high-frequency characteristics of glass laid strong pathways for Advanced Packaging Roadmaps. However, insertion of glass poses several challenges such as CD uniformity of Through Glass Via (TGV) etch over different aspect ratio of via sizes. Also due to the CTE mismatch between glass and metal, adhesion and stress management appears to be a huge issue for integration of TGV metallization and RDL layers. This paper presents the detail of TGV etch process with respect to different glass types, laser modification methods, and aspect ratio. Etching characterization over bath life as well as with various Design of Experiments (DOE) was performed to address the HVM challenges. Fabrication of TGV and metallization requires a good buffer layer (BL) on glass vias followed by Eless Cu deposition. Based on the types and properties of buffer layer, buffer layer serves the purpose of adhesion promotion liner (APL) as well as stress buffer layer (SBL). Additionally, Electrode less (Eless) Cu would be beneficial to provide as seed layer for conformal or full TGV metallization. Hence, a closer look into the development of Through Glass Via (TGV) processing, Adhesion promotion layer (APL), and Eless Cu techniques are discussed in this paper. A Wet process system has been developed to enable the TGV processing, Adhesion promotion, and Eless Cu for different types of glass substrates. Cross sectional and chemical analyses were done to validate the studies and the data were used to develop the glass etching, APL/SBL, and Eless Cu. Simulation and experimental data indicates that this approach is feasible to address glass processing and stress management challenges.

At present, perforation of high aspect ratio through glass vias (TGVs) is one of the primary factors limiting the development of glass interposers. Herein, it is based on a large number of experiments, combined with mechanistic analysis, to realize the perforation of ultrahigh/high aspect ratio fused silica TGVs using selective laser‐induced etching. First, the effect of the number of pulses as well as other laser parameters on the etching selectivity is systematically investigated. It is found that the formation of nanochannels in fused silica is crucial in determining the high selectivity. Subsequently, a model based on diffusion theory is proposed to mathematically explain the reasons for the high selectivity generation. Finally, the perforations of TGVs with diameters of 5.4–26.4 μm, aspect ratios of 11.7–61.3, and vertical sidewalls are achieved, at a laser treatment speed of ≈10 000 TGVs per minute. This research can serve as an essential reference for the manufacturing of TGVs with high aspect ratios and glass interposers with high interconnection density.

As electronic products become smaller and thinner with increasing number of functions, the demand for high density and high integration becomes stronger. Glass has many properties that make it an ideal substrate for high integration substrate such as; ultra high resistivity, adjustable thermal expansion (CTE) high modulus, low dielectric constant, low dielectric loss and manufacturability with large panel sizes. Multi-bands with carrier aggregation, Wi-Fi/GPS coexistence, and LTE-U make RF front end more and more complicated. 3D IPD (integrated passive devices) on Glass substrate technology could be advantage solution include reducing power consumption and small form factor. This paper presents a demonstration of 3D RF front end filters using 3D solenoid inductors with through glass vias (TGV) and Cu-SiN-Cu MIM structure on Gen1 glass substrate (300mm × 400mm) panel format using color filter manufacturing line for flat panel display. For inductors, drastic performance (size and low resistance therefore high-quality factor) improvement have been demonstrated by technology evolutions from 3D solenoid using TGV with conformal Cu plating method, achieving low resistance of 3.1mohm per 70um diameter TGV on a 400um thick glass panel. This low-resistance TGV with 2.7mOhm/sq TGV connections on both sides of the glass substrate, record high inductor quality factor of 39 was obtained at 2.5GHz using five and half turn inductor of 7.9nH inductance, For capacitors, we have successfully integrated a Cu MIM (metal-insulator-metal) structure by using 15um thick Cu plates and dielectric, resulting in high capacitance density of 0.26nF/mm2 for RF application. By integrating TGV inductor-first and MIM capacitor-next, high-performance and high-density LC components are synthesized to perform as RF front end filters such as low-pass filters, diplexers, triplexers, and multiplexers. The 3D inductors, Cu MIM, LC resonators and filters were successfully integrated using glass panel manufacturing infrastructure for the first time. Process characterization and process control monitors were evaluated at the panel level to address high-volume and high-yield manufacturability of RF filters with the unprecedented filter performance in terms of insertion loss and out of band rejections in smaller form factor than any other technologies have achieved so far. Furthermore, the TGV filters were mounted on electrical evaluation boards as well as JEDEC standard testing boards to check any device-level, chip-level, and board-level reliabilities associated with glass or TGV materials as well as their interaction with Cu, SiN, polymer inter layer dielectric materials, and solder joints, showing no performance degradations during thermal cycling, drop shock, bending, or high-power testing situations.

Through Glass Vias (TGV) interconnection has important application and development in 2.5D package, especially for interposers. Compared with through silicon vias (TSV), the coefficient of thermal expansion is well matched to wafer. Also, TGV interposer has less dielectric loss when transmitting high-frequency signals. The electrodeposition of through-holes (THs) is a key step, especially at a fast speed. In this research, typical tapered THs with double-sided seed layers were filled by copper electroplating, which has an aspect ratio of 3: 1 and diameter of 50 μm. Double anode plating method is used to achieve void-free filling under different current densities. The test results of scanning electron microscopy confirm the surface and cross section quality of electroplating. With the synergistic effect of particular inhibitor A, accelerator B and leveler C which ratio is 60:1:1, we can fill the THs without voids at a current density of 1.5ASD in 1.5 hours, along with smoother coating surfaces and uniformity of two coating surfaces.

In recent years, glass interposer has emerged as a superior alternative to organic and silicon-based interposers for advanced 2.5D or 3D IC, due to its attractive advantages such as excellent electrical isolation, better radio frequency performance, better feasibility with the CTE and could be fabricated with large size. However, the warpage for wafer level 2.5D or 3D packaging using glass interposer is a serious issue. In this paper, A new type of 3D wafer level packaging for MEMS based on glass interposer is presented and the warpage during the molding process is investigated based on finite element simulation. The effect of different material parameters and thickness of glass on warpage characteristics is investigated. The results show that when the CTE increases from 3 ppm/°C to 10 ppm/°C for glass interposer, the wafer warpage variation from “smile” to “cry”. Our experiments indicated that the optimized glass interposer successfully passed the reliability test of precondition level 3. It is a conclusion that the process flow of the glass interposer and FEM simulation process offers a significant reference for 3D product applications. Moreover, in the next step, we will discuss how to modify the material parameters and thickness of the EMC to improve the performance of the glass interposer.

The electrical characteristics of silicon and glass interposer channel are heavily affected by the design of through silicon via (TSV) and through glass via (TGV). In this paper, we analyzed the overall signal integrity of glass and silicon interposer channel including through package via. To compare electrical property between silicon and glass, we simulated these channels in frequency-domain and time-domain. We observed s-parameter of single and multiple via transition channel. Moreover we compared the characteristic impedance and eye diagram simulation results. Finally, we observed the change of electrical characteristics when the impedance mismatch is occurred at via pad.

Glass is an ideal substrate material to enable 2.5D and 3D packaging of ICs at low cost and high performance. However, it is a brittle material and is prone to failures during fabrication and operation. Large coefficient of thermal expansion (CTE) mismatch between copper and glass leads to thermomechanical stresses that can lead to glass cracking and delamination from glass interfaces. This paper focuses on modeling and reliability characterization of copper-plated through-package-vias (TPV) in glass packages. Thermomechanical simulations were carried out to obtain design guidelines for reliable TPVs in glass. Test-vehicles with different glass thicknesses and copper TPV fabrication conditions were fabricated for thermal cycling tests, resistance monitoring and failure analysis. The reliability characterization results showed good thermomechanical reliability of TPVs in ultra-thin glass panels.

A previously presented topside Cu-filled through-glass-via channel (a “Cu bridge”) is expected to be better able to support high-speed high-density signal processing in multi-chiplet systems than Cu through-glass vias based on existing electroplating techniques (conformal filling and bottom-up filling). Large-scale processing of glass interposers embedded with these Cu bridges has now been demonstrated using both a glass panel ( $300 \text{mm} \times 400 \text{mm}$ ) and a glass wafer (300 mm diameter) as another step towards achieving high-volume mass production of a glass interposer embedded with these bridges. For as many as 10 million Cu bridges embedded in the panel ( $100-\mu\mathrm{m}$ -pitch fully arrayed through-glass via), there were no via-opening or via-filling failures. The thermal stability of the Cu bridge against thermal stressing was demonstrated by thermal cycle testing with electrical inspection. The simulated heat dissipation and signal transmission capabilities of a glass interposer embedded with Cu bridges were comparable those of a silicon interposer. The cost of manufacturing the glass interposer is estimated to be up to 53% less than that for a silicon interposer.

This presentation will discuss TGV market trends and a low cost solution using new glass and synthetic fused quartz materials, TCE matched Cu metalizations, and designs for high density interconnect. The glass substrate or wafer combined with the low cost Cu metalization offers the market a solution that it has not yet seen. Applications are MEMS devices, Signal processing devices, memory storage devices, where hermeticity and high reliability are required, but the real challenge is how to achieve this at low cost. TGV technology offers significant advantages over Through Silicon Via (TSV) techniques, in that the glass can be assembled with the Si wafer or as a die with several highly reliable bonding techniques, which will be discussed. Technology continues to evolve requiring form factors that are smaller and smaller while still maintaining high frequency performance and long battery life; which are driving more interconnects from single IC's. Glass Interposers offer a high aspect ratio of wafer/substrate thickness to via diameter, and this paper will demonstrate 25–50micron vias in 10–15mil thick glass or synthetic fused quartz using low cost methods of production. While this method may be disruption to the current TSV supply chain to IC Device manufacturers, it will offer them a low cost, highly reliable solution they seek. The solution is enabled by an AGC manufactured Synthetic Quartz using a patented process that facilitates low impurities levels which results in an insertion loss previously unavailable at in both polymeric substrates and ceramic substrates.

As a result of their myriad of advantages over silicon and other conventional substrate technologies, glass substrates have received significant attention from the electronic packaging and system integration community worldwide. So far, most of the research effort on glass has concentrated on developing methods for fabricating cylindrical through glass vias (TGVs). However, to fully evaluate the potential of glass as an interposer material for microelectronic systems with computing and communication functions, an extensive characterization of interconnects and RF components on these substrates must be carried out. In this contribution, we go beyond state-of-the-art research and present an in-depth characterization of TGVs, coplanar lines and 60 GHz coplanar excited patch antennas on two glass substrates. One of these substrates has a low alkaline content (Borofloat33®) and the other is alkaline-free (AF32®). The effects of these glass materials on the RF performance of TGVs, coplanar lines and 60 GHz antennas are extensively studied, and recommendations for performance optimization are proposed. For experimental verification, test samples are fabricated and measured. Very good correlation is obtained between the measurement and simulation results from 100 MHz to 100 GHz.

The corrugated layer structure bismuth has been successfully tailored into negative thermal expansion along c axis by size effect. Pair distribution function and extended X-ray absorption fine structure are combined to reveal the local structural distortion for nanosized bismuth. The comprehensive method to identify the local structure of nanomaterials can benefit the regulating and controlling of thermal expansion in nanodivices.