Offline Phase Analysis and Optimization for Multi-configuration Processors

The improvement for energy efficiency has been increasingly becoming a major consideration in server and data center design, especially for the power-hungry ones. Numerous studies have provided various new methods or proposals for the building of green server and data center, but this paper concentrates on how different configuration schemes in a server effect practical performance and power consumption for specific applications. It is completely necessary to obtain thin provisioning for the particular applications to meet performance requirements with minimal energy consumption. This paper evaluates the different hardware configurations' impact on energy consumption and performance for typical applications, hoping for offering evidences or clues to subsequent researches. The File Bench is used to generate four sever workloads and ZH-101 is employed to collect relevant real-time power consumptions. Our result shows that different workloads need different hardware configurations at the demands of both energy-efficiency and performance. And running multiple workloads on a reduced hardware configuration is a wise choice.

Energy is becoming a key resource for IT systems. Hence, it can be essential for the success of a system under development to be able to derive and optimise its resource consumption. For large IT systems, compositionality is a key property in order to be applicable in practice. If such a method is hardware parametric, the effect of using different algorithms or running the same software on different hardware configurations can be studied. This article presents a hardware-parametric, compositional and precise type system to derive energy consumption functions. These energy functions describe the energy consumption behaviour of hardware controlled by the software. This type system has the potential to predict energy consumptions of algorithms and hardware configurations, which can be used on design level or for optimisation.

Recent work has demonstrated that, cache space is often poorly utilized. However, no previous work has yet demonstrated upper bounds on what a cache or local memory could achieve when exploiting both spatial and temporal locality. Belady's MIN algorithm does yield an upper bound, but exploits only temporal locality. In this article, we present an optimal replacement algorithm for local memory that exploits temporal locality and spatial locality simultaneously. This algorithm is an extension of Belady's algorithm. We prove the optimality of this new algorithm with respect to minimizing misses, and we show experimentally that the algorithm produces nearly minimum memory traffic on the SPEC95 benchmarks. Like Belady's algorithm, our algorithm requires the entire program trace. It selects replacement victims and the number of words it fetches at once based on future accesses. Many different spatial locality strategies can be implemented with this algorithm. With an optimal strategy, the algorithm yields an upper bound that enables us to evaluate alternative implementations to today's caches. We further demonstrate the utility of this algorithm as an analysis tool by evaluating several intermediate strategies between cache and optimal to highlight the limitations of the cache line paradigm using the SPEC95 benchmarks.

We present a Concurrent Error Detection (CED) scheme for the Scheduler of a modern microprocessor. The proposed CED scheme is based on monitoring a set of invariances imposed through added hardware, violation of which signifies the occurrence of an error. The novelty of our solution stems from the workload-cognizant way in which these invariances are selected so that they leverage the application-level error masking inherent in program execution. Specifically, in order to ensure cost-effectiveness of the hardware employed to construct these invariances, we make use of information regarding the type and frequency of errors affecting the typical workload of the microprocessor. Thereby, we identify the most susceptible aspects of instruction execution and we accordingly distribute CED resources to protect them. Our approach is demonstrated on the Scheduler of an Alpha-like superscalar microprocessor with dynamic scheduling, hybrid branch prediction and out-of-order execution capabilities. Using an extensive fault-simulation infrastructure that we developed around this microprocessor, we profile the impact of Scheduler faults across a variety of different SPEC2000 benchmarks. Based on the results, we construct a CED scheme which monitors the time and location of instruction execution, the executed operation, the utilized resources, as well as the executed and retired sequence of instructions. At a hardware cost of only 32 percent of the Scheduler, the corresponding CED scheme detects over 85 percent of its faults that affect the architectural state of the microprocessor. Furthermore, over 99.5 percent of these faults are detected before they corrupt the architectural state, while the average detection latency for the remaining faults is in the order of a few clock cycles, implying that efficient recovery methods can be developed.

Techniques and tools for verification of multi-threaded programs must cope with the huge number of possible thread interleavings. Tools based on systematic exploration of a program state space employ partial order reduction to avoid redundant thread interleavings. The key idea is to make non-deterministic thread scheduling choices only at statements that read or modify the global state shared by multiple threads. We focus on the approach to partial order reduction used in tools such as Java Pathfinder (JPF), which construct the program state space on-the-fly, and therefore can use only information available in the current program state and execution history to identify statements that may be globally-relevant. In our previous work, we developed a field access analysis that provides information about fields that may be accessed during program execution, and used it in JPF for more precise identification of globally-relevant statements. We build upon that and propose a may-happen-before analysis that computes a sound approximation of the happens-before ordering. Partial order reduction techniques can use the happens-before ordering to detect pairs of globally-relevant field access statements that cannot be interleaved arbitrarily (due to thread synchronization), and based on that avoid making unnecessary thread scheduling choices. The may-happen-before analysis combines static analysis with knowledge of information available from the dynamic program state. Results of experiments with several Java programs show that usage of the may-happen-before analysis further improves the performance of JPF.

An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dual-rail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches.

In this paper, we analyze the issues of power control and cell discontinuous transmission in a small-cell network. More precisely, we evaluate the performance of a policy, thanks to which each base station minimizes its own energy consumption. We have recently proposed this policy in a mono-cell scenario and we extend the scope of our previous work in this article, as we propose to use this policy in a multi-cell network. For that purpose, we first consider a network made of two base stations, in which we can compute the minimum network’s energy consumption, which enables to provide users with the requested quality of service. If we compare the proposed policy with this minimum, we can demonstrate that the proposed policy has a good performance, which, however, can be improved by reducing the maximum transmit power of the base station. Then, we apply our algorithm in the case of a dense network, in which the proposed policy outperforms other policies and provides a 6% gain in energy, where compared to a policy featuring no power control. We show that the reduction of the maximum transmit power can increase this gain up to 11% of the network’s energy consumption.

In this dissertation, we address the problem of performance efficient multithreading execution on heterogeneous multicore embedded systems. By heterogeneous multicore embedded systems we refer to those, which have real-time requirements and consist of processor tiles with General Purpose Processor (GPP), local memory, and one or more coprocessors running on reconfigurable logic ((e)FPGA). We improve system performance by combining two common methods. The first method is to exploit the available application parallelism by means of multithreading program execution. The second method is to provide hardware acceleration for the most computationally intensive kernels. More specifically our scientific approach is as follows: we categorize the existing program execution models from the processor-coprocessor synchronization prospective and we introduce new parallel execution models. Then, we provide a high-level architectural abstraction of those execution models and programming paradigm that describes and utilizes them. Furthermore, we propose a microarchitectural support for the identified execution models. The functionality of the microarchitectural extensions is encapsulated in a new reconfigurable coprocessor, called Thread Interrupt State Controller (TISC). To improve the overall system performance, we employ the newly proposed program execution models to transfer highly time-variable and time-consuming Real-Time Operating System (RTOS) and application kernels from software, i.e., executed on the GPPs, to hardware, i.e., executed on the reconfigurable coprocessors. We refer to this reconfigurable coprocessor as Hardware Task Status Manager (HWTSM). Due to the properties of the newly introduced execution models such as parallel execution and constant response time, we preserve the predictability and composability at application level. Last but not least, we introduce a framework for distribution of slack information (idle processor time) among processor tiles. In the proposed framework we employ one of the newly introduced parallel processor-coprocessor execution models. We refer to the new reconfigurable coprocessor as RS. We use the extra slack information obtained through our framework for Dynamic Voltage Frequency Scaling that reduces the overall energy consumption. Based on the available experimental results with synthetic and real applications, we improve the system speedup up to 19.6 times with the help of the Thread Interrupt State Controller. Furthermore, we reduce RTOS cost with the help of the Hardware Task Status Manager, which results in additional application acceleration up to 13.3%. Last but not least, we improve the system energy consumption up to 56.7% over current state of the art with the help of inter-tile remote slack information distribution framework. Overall, with the help of our contributions, the system performance is improved, the predictability and composability are preserved, all with reduced energy consumption.

A quantitative analysis of program execution is essential to the computer architecture design process. With the current trend in architecture of enhancing the performance of uniprocessors by exploiting fine-grain parallelism, first-order metrics of program execution, such as operation frequencies, are not sufficient; characterizing the exact nature of dependencies between operations is essential. This paper presents a methodology for constructing the dynamic execution graph that characterizes the execution of an ordinary program (an application program written in an imperatibve language such as C or FORTRAN) from a serial execution trace of the program. It then uses the methodology to study parallelism in the SPEC benchmarks. We see that the prallelism can be bursty in nature (periods of lots of parallelism followed by periods of little parallelism), but the average parallelism is quite high, ranging from 13 to 23,302 operations per cycle. Exposing this parallelism requires renaming of both registers and memory, though renaming registers alone exposes much of this parallelism. We also see that fairly large windows of dynamic instructions would be required to expose this parallelism from a sequential instruction stream.

Finding the best energy-performance tradeoffs for High Performance Computing (HPC) applications is a major challenge for many modern supercomputing centers. With the increased focus on data center energy efficiency and the emergence of possible data center power constraints, making the right decision at a given time is becoming more important. A real-world situation like can a given 1000 compute node application be executed at a maximum of 2.7 GHz CPU frequency without going over the energy provider defined power band, or the available monthly energy limit? is just one example of the types of decisions HPC data centers will face. The previously developed Adaptive Energy and Power Consumption Prediction (AEPCP) model answers this question for the case of a fixed CPU frequency. This paper will extend the AEPCP process to enable the development of analytical models for estimating application execution time, power, and energy consumptions as functions of the number of compute nodes and maximum operating CPU frequency. Based on these analytical models, an adaptive model (Lightweight Adaptive Consumption Prediction (LACP)) is presented that implements the extended prediction process. This information allows for improved estimation of potential energy-performance costs and tradeoffs of applications and thus identifies the optimal resource configuration for specific data center boundary conditions.

Long range (LoRa) is a wireless communication standard specifically targeted for resource-constrained Internet of Things (IoT) devices. LoRa is a promising solution for smart city applications as it can provide long-range connectivity with a low energy consumption. The number of LoRa-based networks is growing due to its operation in the unlicensed radio bands and the ease of network deployments. However, the scalability of such networks suffers as the number of deployed devices increases. In particular, the network performance drops due to increased contention and interference in the unlicensed LoRa radio bands. This results in an increased number of dropped messages and, therefore, unreliable network communications. Nevertheless, network performance can be improved by appropriately configuring the radio parameters of each node. To this end, in this article we formulate integer linear programming models to configure LoRa nodes with the optimal parameters that allow all devices to reliably send data with a low energy consumption. We evaluate the performance of our solutions through extensive network simulations considering different types of realistic deployments. We find that our solution consistently achieves a higher delivery ratio (up to 8% higher) than the state of the art with minimal energy consumption. Moreover, the higher delivery ratio is achieved by a large percentage of nodes in each network, thereby resulting in a fair allocation of radio resources. Finally, the optimal network configurations are obtained within a short time, usually much faster than the state of the art. Thus, our solution can be readily used by network operators to determine optimal configurations for their IoT deployments, resulting in improved network reliability.

More and more applications need The ability to customize the architecture to match the computation and the data flow of the application, so increasingly new system implementations based on reconfigurable computing are being considered. Reconfigurable computing has potential to accelerate a wide variety of applications; its main feature is the ability to perform computations in hardware to improve performance, while retaining the flexibility of software solutions. An operating system (OS) for reconfigurable computing uses new versions of algorithms for the scheduling, the operating system must decide how to allocate the hardware at run-time based on the status of the system. This paper discusses the scheduling algorithm for reconfigurable computing platform, covers two aspects of reconfigurable computing: architectures and design methods. The tasks are divided into two categories in this survey, consider the issues involved in reusing the configurable hardware during program execution. And improve μC/OS-II to manage the use of reconfigurable resources, responsible for task scheduling, helping the programmer to concentrate more on application development.

Conceptual Development, Analysis and Simulation of the Transport Capacity of a Freight Transport Vehicle in Vacuum Tubes at High Speed (Hyperloop Concept)

Assessing Lighting Energy Saving Potential from Daylight Harvesting in Office Buildings Based on Code Compliance & Simulation Techniques: A Comparison

Process modelling and optimization of a 250 MW IGCC system: ASU optimization and thermodynamic analysis