On Bias in Transition Coverage of Test Sets for Path Delay Faults

Skewed-load and broadside tests complement each other and allow higher delay fault coverage to be achieved for a standard-scan circuit that supports both types of tests. The difference between the two types of tests is mainly in the test application process. The input test data required for both of them are similar. This similarity is used in this work to compute compact input test data that can be used as a basis for forming both types of tests. It results in improved fault coverage compared to the use of broadside (or skewed-load) tests alone, and in reduced test data volume compared to the case where broadside and skewed-load tests are stored separately. Experimental results are presented using a procedure that accepts a test set of any type, and computes input test data suitable for the application of both types of tests. The procedure modifies the test data so as to compact it as well as increase the fault coverage. The procedure is applied to a broadside test set and to mixed test sets that consist of both types of tests.

The use of both broadside (launch-on-capture) and skewed-load (launch-on-shift) tests for delay faults results in increased delay fault coverage and better test compaction than the use of a single test type. Two-cycle broadside and skewed-load tests differ in the sequence of length two applied to the scan-enable input between the scan-in and scan-out operations of a test. Considering a circuit with a single clock domain, the question that this article attempts to answer is whether it is possible to generate a complete test set for transition faults where all the tests use the same scan-enable sequence of length three or more. The use of a single scan-enable sequence simplifies the test application process. Experimental results demonstrate that there is a significant number of benchmark circuits for which a test set with a single scan-enable sequence achieves the same transition fault coverage as a test set that consists of both broadside and skewed-load tests. For other benchmark circuits, a small loss in transition fault coverage compared with the use of both test types allows a single scan-enable sequence to be used.

Two-pattern tests for delay faults in standard scan circuits can be of one of two types: skewed-load or broadside. Each type of tests creates different conditions during test application due to the different way in which scan mode and functional mode are interleaved. Therefore, tests that are applicable both as skewed-load tests and as broadside tests are useful for comparing the two types of tests with respect to properties such as defect coverage or overtesting. In this work we investigate the possibility of generating tests that are applicable under both test application schemes. We refer to two-pattern tests that are applicable as both skewed-load and broadside tests as common-mode tests. We show that most benchmark circuits have sufficient numbers of common-mode tests to make them an interesting class of tests. Moreover, we show that the use of multiple scan chains increases the number of common-mode tests.

This paper studies the effect of the type of scan-based delay fault tests used for a circuit on the ability to diagnose delay defects by studying its effect on diagnosis of transition faults. The authors consider enhanced scan tests, skewed-load tests, broadside tests, functional broadside tests, and a combination of skewed-load and broadside tests. The results indicate that while functional broadside tests should be used for fault detection to avoid overtesting, the test set should be extended for fault diagnosis by adding other types of tests. Adding a small number of skewed-load tests is especially useful for diagnosis if enhanced scan is not available

Tester limitations may impose certain constraints on the primary input vectors applicable as part of a two-pattern test for delay faults. Under these constraints, the primary input vectors may be held constant, or the second primary input vector of a test may be obtained by a single shift of a scan chain relative to the first. The goal of this brief is to study the differences in achievable transition fault coverage between various primary input constraints that are similar to the commonly used ones of holding or shifting primary input vectors. This brief also studies the possibility of combining the constraints in order to increase the transition fault coverage. The combination requires a fixed and circuit-independent hardware structure similar to the case where shifting of primary input vectors is used. This study is done using test sets that consist of both broadside and skewed-load tests in order to maximize the transition fault coverage.

The use of multiple scan chains was shown to improve the coverage of transition faults achieved by skewed-load tests. For broadside tests, the number of scan chains does not affect the transition fault coverage. We describe an enhanced broadside configuration under which increasing the number of scan chains helps increase the fault coverage. In the enhanced configuration, the first flip-flop of a scan chain operates in skewed-load mode while the other flip-flops operate in broadside mode. This provides flexibility in determining the value of the first flip-flop of every scan chain under the second pattern of a broadside test, thus increasing the transition fault coverage. We also describe a procedure that makes small modifications to a given scan chain configuration in order to improve the transition fault coverage.

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure.

Functional broadside tests address overtesting due to high-power dissipation by creating functional operation conditions during the clock cycles where delay faults are detected. Guided by their switching activity, it is possible to generate a low-power test set whose switching activity does not exceed the switching activity possible during functional operation. This brief applies the same approach to the generation of a low-power diagnostic test set. Excessively high switching activity can cause unexpected fault effects to appear, which will reduce the accuracy of fault diagnosis. This is avoided with a low-power diagnostic test set. Functional broadside tests are also used for avoiding diagnostic tests with unnecessarily low switching activity. The procedure described in this brief is the first to generate low-power diagnostic tests under functional constraints on switching activity as given by functional broadside tests.

Approximations of functional broadside tests maintain close-to-functional operation conditions in order to avoid overtesting of delay faults. Approximations were used earlier for increasing the fault coverage of functional broadside tests. This paper describes the first procedure that uses an approximation, referred to as piecewise-functional broadside tests, to achieve test compaction. Piecewise-functional broadside tests are characterized by a parameter p. A lower value of p indicates a closer proximity to functional operation conditions. The test compaction procedure combines a pair of tests, t i and t j , to form a test, t i,j , that can replace t i and t j without reducing the fault coverage, and thus reduce the number of tests. With t i and t j having parameter values p i and p j , respectively, the combined test t i,j has parameter value p i,j ≤ p i + p j . The procedure increases the bound p on p i,j gradually as it compacts the test set. Experimental results for benchmark circuits show that significant levels of test compaction can be achieved with p = 2. In addition, the procedure converges for a small value of p.

SAT-based generation of compressed skewed-load tests for transition delay faults

Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such test sets may not detect faults associated with the next-to-longest paths. This may lead to undetected failures since shorter paths may fail without any of the longest paths failing. In addition, paths that appear to be shorter may actually be longer than the longest paths if the procedure used for estimating path length is inaccurate. We propose a test enrichment procedure that increases significantly the number of faults associated with the next-to-longest paths that are detected by a (compact) test set. This is achieved by allowing the underlying test generation procedure the flexibility of detecting or not detecting the faults associated with the next-to-longest paths. Faults associated with next.-to-longest paths are detected without increasing the number of tests beyond that required to detect the faults associated with the longest paths. The proposed procedure thus improves the quality of the test set without increasing its size.

Design-for-testability (DFT) for synchronous sequential circuits allows the generation and application of tests that rely on non-functional operation of the circuit. This can result in unnecessary yield loss due to the detection of faults that do not affect normal circuit operation. Considering single stuck-at faults in full-scan circuits, a test vector consists of a primary input vector U and a state S .We say that the test vector consisting of U and S relies on non-functional operation if S is an unreachable state, i.e., a state that cannot be reached from all the circuit states. Our goal is to obtain test sets with states S that are reachable states. Given a test set C, the solution we explore is based on a simulation-based procedure to identify reachable states that can replace unreachable states in C. No modifications are required to the test generation procedure and no sequential test generation is needed. Our results demonstrate that the proposed procedure is able to produce test sets that detect many of the circuit faults, which are detectable using scan, and practically all the sequentially irredundant faults, by using test vectors with reachable states. The procedure is applicable to any type of scan-based test set, including test sets for delay faults.

A study is presented concerning the efficiency of test pattern sets generated with the transition fault model applied to fine grained delay fault models. The authors have developed the delay fault simulator DELFI-a program which is capable of simulating timing failures of combinational circuits using different delay fault models. For the computer experiments the authors selected transition fault test pattern sets because they are very cost-effective to generate. The simulations of benchmark circuits demonstrate that the transition fault test patterns detect gross delay faults even at nodes with redundant stuck-at faults. Furthermore the results show that the transition fault test patterns are not sufficient for small delay faults in the range of a few gate delays. In order to receive a satisfactory coverage for these delay faults, the transition fault test sets must be extended. >

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. In addition, it can potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of handling large numbers of paths. A parameter called Δ is used to control the number of funtional faults targeted and thus the number of tests generated. If Δ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. An appropriate subset of tests can be selected once the implentation is known. The test sets generated for various values of Δ are fault simulated on gate-level realizations to demonstrate their effectiveness. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.

With the increased densities of integrated circuits, several different types of faults can occur. Faults in digital circuits resulting from random defects can introduce DC (stuck-at) faults as well as AC (delay) faults. Previous work in statistical modeling and analysis for delay fault testing generally assumes that at most a single delay fault can occur along any given path in the circuit under test. In this paper we investigate the statistical effect of multiple delay faults along any path in a circuit under test, and predict the path delay fault probabilities as well as the maximum number of path delay faults for both combinational and sequential benchmark circuits. We begin with the development of a statistical model for path delay faults in VLSI circuits [4], which takes into account multiple delay faults along any signal path.