On-Chip Copper-Based vs. Optical Interconnects: Delay Uncertainty, Latency, Power, and Bandwidth Density Comparative Predictions

The rapid scaling of microprocessor technologies has led to unprecedented advancements in processing speed and transistor density. However, as device dimensions shrink below the nanometre scale, traditional electrical on-chip interconnects face critical limitations including increased signal delay, power consumption, and reduced bandwidth. These challenges have emerged as major bottlenecks in the performance and energy efficiency of modern microprocessors, especially in multi-core and many-core architectures. To overcome these limitations, optical interconnects have gained significant attention as a high-performance alternative for on-chip and chip-to-chip communication. Optical interconnects offer key advantages such as higher data rates, lower latency, reduced power dissipation, and immunity to electromagnetic interference. The integration of optical components like waveguides, modulators, photodetectors, and silicon photonics within the chip architecture has the potential to revolutionize interconnect design by addressing the shortcomings of conventional electrical wiring. This paper explores the evolution of on-chip interconnects, comparing the performance, scalability, and integration challenges of electrical and optical solutions in scaled microprocessors. It also discusses emerging hybrid interconnect architectures that combine the strengths of both technologies. A comparison is made between electrical and optical interconnects for different design criteria, based on projections about the future of optical devices. Around a tenth of the length of the chip's edge is the crucial dimension beyond which optical connectivity becomes preferable to electrical interconnect at the 22 nm technological node.

In this paper, the opportunity of replacing on-chip electrical interconnects with optical interconnects in general purpose high performance applications is evaluated by simulations in the ITRS scaling scenario. Speed and energy consumption of a point-to-point on-chip optical interconnect link are benchmarked against on-chip electrical interconnects options optimized at circuit level for serving high performance applications. Since the on-chip optical interconnect technology is not mature yet in all its necessary link components, reasonable assumptions are taken and extrapolated in the ITRS scaling scenario.

We present an array of electro-optic Bragg gratings for on-chip optical waveguide interconnect applications. These electro-optical gratings can serve as switchable couplers to couple high-speed optical signals from a vertical cavity surface emitting lasers (VCSEL) to on-chip polymeric waveguides and from waveguides to photodetectors. The unique switching feature provides a promising solution to facilitate dynamically reconfigurable on-chip optical interconnects architecture for intra-chip, chip-to-chip and board-to-board data communications. We demonstrate on-chip switched optical waveguide interconnect using electro-optic grating and polymeric channel waveguides on a silicon substrate.

We discuss our recent work on mode division multiplexing (MDM) silicon devices for on-chip optical interconnects. First, we demonstrate a 4-channel MDM device based on directional couplers. The crosstalk values are below -13.3 dB at 1550 nm for the TE0, TM0, and TM1 channels. The TE1 channel experiences the largest crosstalk at 1553 nm of -6.5 dB and the highest loss of 2.6 dB. Four channels of 40Gb/s signals in the form of 20-Gbaud quadrature phase shift keying (QPSK) are multiplexed through MDM to test the device The 160-Gb/s data is transmitted through a multi-mode waveguide and then de-multiplexed for bit-error ratio (BER) measurement. By using multiple-input multiple-output (MIMO) digital processing, error free operation is achieved. Second, to further increase the capacity, we design and implement an 11-channel MDM device by employing subwavelength grating (SWG) couplers. The main limiting factor in the number of MDM channels is the susceptibility of the effective waveguide refractive index to the width variation due to the fabrication errors, and the index curves of for the multi-mode bus waveguide and the single mode access waveguide are of different slopes. Through index engineering by duty cycle optimization of the SWG access waveguide, the index curves of the two different waveguides can be matched and thus the phase matching condition in the MDM process is maintained with the similar fabrication errors imposed on the two waveguides. The crosstalk values of such a SWG based 11-channel MDM device remain lower than -7 dB for all channels, and the loss is below 13.7 dB for the worst channel. We then use 30-Gbaud 16-quadrature amplitude-phase modulation (QAM) signals to test the device, and the BERs are below the 7% feedforward error correction threshold after MIMO processing. A total transmission capacity of 1.23 Tb/s on a single wavelength is achieved.

To meet the demand for light sources for on-chip optical interconnections, we demonstrate the continuous-wave (CW) operation of photonic-crystal (PhC) nanocavity lasers at up to 89.8°C by using InP buried heterostructures (BH). The wavelength of a PhC laser can be precisely designed over a wide range exceeding 100nm by controlling the lattice constant of the PhC. The dynamic responses of the PhC laser are also demonstrated with a 3-dB bandwidth of over 7.0GHz at 66.2°C. These results reveal the laser's availability for application to wavelength division multiplexed (WDM) optical interconnection on CMOS chips. We discuss the total bandwidths of future on-chip optical interconnections, and report the capabilities of PhC lasers.

Optical interconnects and carbon nanotubes (CNTs) present promising options for replacing the existing Cu-based global/semiglobal (optics and CNT) and local (CNT) wires. We quantify the performance of these novel interconnects and compare it with Cu/low-kappa wires for future high-performance integrated circuits. We find that for a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. For semiglobal and global wires, we compare both optical and CNT options with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. Optical wires have the lowest latency and the highest possible bandwidth density using wavelength division multiplexing, whereas a CNT bundle has a lower latency than Cu. The power density comparison is highly switching activity (SA) dependent, with high SA favoring optics. At low SA, optics is only power efficient compared to CNT for a bandwidth density beyond a critical value. Finally, we also quantify the impact of improvement in optical and CNT technology on the above comparisons. A small monolithically integrated detector and modulator capacitance for optical interconnects (~10 fF) yields a superior power density and latency even at relatively lower SA (~20%) but at high bandwidth density. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient.

We propose a new approach to the physical design of optoelectronic system-on-a-package (SOP) using optical waveguide interconnect technology. The objective is to improve the performance of SOP by replacing long distance electrical interconnects with optical waveguide interconnects. A new simultaneous optimization algorithm for module placement and routing of electrical and optical interconnects is introduced. It not only improves the performance of SOP, but reduces the simulation time. Even though a small portion of electrical interconnects are replaced with optical interconnects, more than 21% improvement of the SOP performance is achieved.

Increasing delay of interconnects over devices at advanced nodes indicates a need for drastic change for interconnect. Such drastic changes have traditionally been possible through material changes. However, an alternative change in design may be near. In particular, on-chip optical interconnections are on the verge of being introduced to be able to cope with system-scale performance roadmaps. Thereby, photon-based information transfer may take the place of charge-based transfer that has been utilized within and across semiconductor chips for decades. Such a change would trigger significant updates to the design flows and circuitry.

We discuss recent progress and challenges in realizing Bragg-grating devices on the submicron silicon-on-insulator platform for next-generation optical communications applications, such as on-chip optical interconnects and signal processing. In particular, we focus on grating-assisted, wavelength-selective couplers, known as contra-directional couplers (contra-DCs). In contrast to conventional two-port Bragg gratings operating in the reection mode, contra-DCs are four-port devices with very weak backreections and, therefore, can be easily integrated with other photonic components on a chip. In order to provide a reliable on-chip wavelength-division multiplexing (WDM) solution for high-speed optical interconnects, we have developed high-performance add-drop filters and, furthermore, wavelength multiplexers/demultiplexers with combined advantages of at-top responses, low insertion loss (< 1 dB), and low crosstalk (< -23 dB). These WDM devices are ultra-compact and highly tolerant to temperature uctuations (up to ±50 °C), showing great potential for large-scale integration and low-power consumption. We further discuss a novel four-port Bragg photonic resonator for high-speed, low-power optical switching. Using a coupler-chirped design with uniform Bragg gratings, we have recently achieved an on-chip, continuously tunable photonic delay line with low insertion loss. These system-orientated devices indicate great potential for large-scale integration of Bragg-grating-defined functions using CMOS-compatible silicon photonics technology.

We demonstrate an electrically-pumped hybrid silicon microring laser fabricated by a self-aligned process. The compact structure (D = 50 microm) and small electrical and optical losses result in lasing threshold as low as 5.4 mA and up to 65 degrees C operation temperature in continuous-wave (cw) mode. The spectrum is single mode with large extinction ratio and small linewidth observed. Application as on-chip optical interconnects is discussed from a system perspective.

The present and the potential performances of opto-electronic elements such as a laser diode (LD), a photo diodes (PD) and an optical waveguide for optical interconnects are described. The fabrication and the integration technologies of the opto-electronic chips are also mentioned. The topics to be highlighted include: (1) the state of the art of vertical cavity surface emitting laser diodes for optical interconnects, (2) the performance analysis of the optical interconnects with integrated optical waveguides and free space optics, and (3) opto-electronic integration technology: hybrid-integration technique, receiver and transmitter design for on-chip and intra-chip optical interconnects.

This paper describes the detailed design of an acoustic emission-based micromachined sensor for smart structures applications to assess in-flight structural integrity. This unique sensor approach combines silicon sensor micromachining, conformal optical waveguide technology, and high-speed optical interconnects to measure acoustic emission event data related to structural failure. A micron-level dual-element micromachined cantilever beam architecture design is described which incorporates conformal on-chip polyimide optical waveguide interconnects to optically sense structural integrity acoustic parameters and route optical power to the sensor assembly. High-speed optical interconnects are used to transfer sensor data to avionic interfaces for debrief and detailed analysis. A detailed design of the optical waveguide sensor design and the significant payoffs and benefits of these sensors are discussed.

Photonic interconnects have potentials to break increasingly severe energy efficiency and bandwidth density bottlenecks of electrical interconnect in scaled complementary metal oxide semiconductor (CMOS) integrated circuits, leading to the emergence of optoelectronic integrated circuits (OEICs) that utilize electronic and photonic devices together in a synergistic way to achieve better performance than those based on pure electronic device technology. By reviewing the progresses of Si-based light-emitting device, the schematic of MOS-like light source integrated with waveguides and the following photodetector is analyzed for its availability. It is believed that on-chip optical interconnects could be achieved by standard CMOS technology successfully with the speed as fast as the velocity of light, supplying propulsions for nest-generation OEICs.

We are delighted to introduce a Special Issue on Optical Interconnects for the IET Optoelectronics magazine. This issue presents the current status as well as some of the outstanding progress that has been witnessed in the rapidly evolving area of optical interconnects. Today, data centres (DC) and high-performance computers are struggling with limited interconnect capacity and increased power consumption while trying to meet overwhelming bandwidth demands. As photonics technologies have been rapidly maturing, optical interconnects have come into the spotlight as the means to cope with the emerging bandwidth, energy, and capacity needs. As such, a wealth of photonic interconnect solutions across the DC hierarchy has unfolded, covering from electro-optic boards to transceiver development, on-chip and on-board switches and interconnects as well as novel noninvasive monitoring methods for light controlling for compensating thermal crosstalk, fabrication tolerances and unstable environmental conditions. At the same time, the increased penetration of optical interconnects in short-reach communications, such as board and chip levels, has triggered new challenges in photonics technologies calling for new innovations with respect to integration techniques and packaging methods. This Special Issue of IET includes integrated circuits, assembly techniques, systems-level architectures, and controlling methods related to short reach ‘chip-to-chip’, ‘in-the-box’, and ‘box-to-box’ communications. Specific areas covered by this special issue include: Silicon photonic transceiver technologies and flat DC topologies; High-speed electro-optic hosting boards and fast, energy-efficient electronics; DC switches and co-packaged optic (CPO) technologies; and Noninvasive controlling techniques for complex photonic integrated circuits. The four papers in this special section promote high-performance optical interconnect architectures and key technologies to tackle the rising bandwidth demands of DCs. They cover (a) co-packaged DC optics, (b) silicon technology transceiver modules and high-speed hosting boards for multisocket server board (MSB) interconnects and (c) automated controlling architecture for complex photonic systems; Items (b) and (c) draw from impressive achievements accomplished through the recently completed European H2020 Project ICT-STREAMS. This report written by C. Mickenberg tries to shed light on motivating factors behind co-packaged optics (CPO), the trade-offs involved and their potential impact on data centre network architectures. The article reviews the evolution of DC switch application-specific integrated circuit (ASICs) and DC optics, provides a future road map and finally discusses the potential impact of CPO on the network architecture. This topic is covered by two articles. The first, written by M. Morallis-Pegios, proposes using silicon photonics to advance interconnect throughput, socket connectivity and energy efficiency in MSB layouts by enabling a flat-topology wavelength division multiplexing (WDM) point-to-point optical MSB interconnect scheme. WDM silicon photonic transceivers coassembled with their electronic circuits achieving a 50-Gb/s line rate and 400-Gb/s aggregate data transmission are demonstrated. The article also proposes silicon photonic Arrayed Waveguide Grating Router (AWGRs) that can offer collision-less time-of-flight connectivity for up to 16 nodes. The second article covering that area is written by T. Lamprecht and reports on the development of electro-optic hosting boards for on-board transceiver subassemblies which is required to eventually form the Tb/s multi-socket onboard communication. The article also discusses the electrical interface as well as photonic board requirements, including the manufacturing technique and the assembly concept that was followed to deliver terabyte per second multichip optical communication. This article, written by F. Zanetto, introduces a novel dithering technique for real-time control of multiple cascaded photonic integrated devices, proposing a calibration-free strategy to support the development and real-life diffusion of increasingly complex photonic systems. The article elaborates on the implementation of a calibration-free automated control loop exploiting integral controllers to close a real-time feedback and stabilise the optimum working point of the employed photonic devices. The effectiveness of the proposed architectural approach is experimentally validated with the error-free routing and transmission of a 30-Gbit/s optical signal traversing a cascade of micro-ring resonator filters. All of the articles selected for this Special Issue present a wide variety of key topics and significant results addressing optical interconnects in high-performance data communication systems, including new progress on architectures, systems and packaging techniques as well as novel optimised controlling methods. As guest editors, we would like to thank all of the authors for their high-quality submissions that significantly contribute to the optical interconnect field. We would also like to thank the reviewers for their valuable and constructive technical comments that greatly enhance the Special Issue, because their feedback and comments ensure the high quality of the IET Optoelectronics Journal. We hope that this IET Special Issue will provide a useful reference of the state-of-the-art in optical interconnects to readers, and we anticipate such technological perspectives will stimulate new advancements and technological outcomes that will in turn enrich the growing field of optical interconnects. This work was supported by the E.C. through the H2020-ICT-STREAMS research project (688172).

Carbon Nanotubes (CNTs), Graphene Nanoribbons (GNRs), and Optical Interconnects and carbon nanotubes present promising options for replacing the existing Cu-based global/semiglobal and local wires. In this chapter, the performance of these novel interconnects is quantified and compared with Cu/low-κ wires for future high-performance integrated circuits. For a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. GNRs outperforms Cu wire below the width of 7nm. For semiglobal and global wires, both optical and CNT options are compared with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density.