On Improving MUS Extraction Algorithms

Minimally Unsatisfiable Subformulas (MUS) find a wide range of practical applications, including product configuration, knowledge-based validation, and hardware and software design and verification. MUSes also find application in recent Maximum Satisfiability algorithms and in CNF formula redundancy removal. Besides direct applications in Propositional Logic, algorithms for MUS extraction have been applied to more expressive logics. This paper proposes two algorithms for computation of MUSes of propositional formulas in Conjunctive Normal Form (CNF). The first algorithm is optimal in its class, meaning that it requires the smallest number of calls to a SAT solver. The second algorithm extends earlier work, but implements a number of new techniques. Among these, this paper analyzes in detail the technique of recursive model rotation, which provides significant performance gains in practice. Experimental results, obtained on representative practical benchmarks, indicate that the new algorithms achieve significant performance gains with respect to state of the art MUS extraction algorithms.

Algorithms for extraction of Minimally Unsatisfiable Subformulas (MUSes) of CNF formulas find a wide range of practical applications, including product configuration, knowledge-based validation, hardware and software design and verification. This pap

This paper explains the design of low cost multi-channel Data Acquisition (DAQ) hardware based on serial communication. The paper puts forward an overall scheme of the system involving the hardware and software design. The hardware design is based on microcontroller (AT89C51) and uses key ADC chip (ADC0808) to realize the acquisition of multichannel analog signals and software design is the implementation of algorithm using the LabVIEW software for acquiring the serial data and presenting the serial data as individual channel data corresponding to measurement for analysis and monitoring in LabVIEW environment.

Automated theorem proving is a method to establish or disprove logical theorems. While these can be theorems in the classical mathematical sense, we are more concerned with logical encodings of properties of algorithms, hardware and software. Especially in the area of hardware verification, propositional logic is used widely in industry. Satisfiability Module Theories (SMT) is a set of logics which extend propositional logic with theories relevant for specific application domains. In particular, software verification has received much attention, and efficient algorithms have been devised for reasoning over arithmetic and data types. Built-in support for theories by decision procedures is often significantly more efficient than reductions to propositional logic (SAT). Most efficient SAT solvers are based on the DPLL architecture, which is also the basis for most efficient SMT solvers. The main shortcoming of both kinds of logics is the weak support for non-ground reasoning, which noticeably limits the applicability to real world systems. The Model Evolution Calculus (ME) was devised as a lifting of the DPLL architecture from the propositional setting to full first-order logic. In previous work, we created the solver Darwin as an implementation of ME, and showed how to adapt improvements from the DPLL setting. The first half of this thesis is concerned with ME and Darwin. First, we lift a further crucial ingredient of SAT and SMT solvers, lemma-learning, to Darwin and evaluate its benefits. Then, we show how to use Darwin for finite model finding, and how this application benefits from lemma-learning.

As clock speed increases taper off and hardware designers struggle to scale parallelism within a chip, software developers and researchers must face the challenge of writing portable software with no clear architectural target. On the hardware side, energy considerations will dominate many of the design decisions, and will ultimately limit what systems and applications can be built. This is especially true at the high end, where the next major milestone of exascale computing will be unattainable without major improvements in efficiency.Although hardware designers have long worried about the efficiency of their designs, especially for battery-operated devices, software developers in general have not. To illustrate this point, I will describe some of the top ways to waste time and therefore energy waiting for communication, synchronization, or interactions with users or other systems. Data movement, rather than computation, is the big consumer of energy, yet software often moves data up and down the memory hierarchy or across a network multiple times. At the same time, hardware designers need to take into account the constraints of the computational problems that will run on their systems, as a design that is poorly matched to the computational requirements will end up being inefficient. Drawing on my own experience in scientific computing, I will give examples of how to make the combination of hardware, algorithms and software more efficient, but also describe some of the challenges that are inherent in the application problems we want to solve. The community needs to take an integrated approach to the problem, and consider how much business or science can be done per Joule, rather than optimizing a particular component of the system in isolation. This will require rethinking the algorithms, programming models, and hardware in concert, and therefore an unprecedented level of collaboration and cooperation between hardware and software designers.

Product Requirement Modeling and Optimization Method Based on Product Configuration Design

Objective To design and implement a universal multi-channel software for neural electrophysiological stimulation experimental platforms. Method The layered design of software and hardware was adopted for the logical architecture to avoid excessive reliance on specific hardware. On the premise of ensuring compatibility with existing devices, an extensible control algorithm based on the. NET Frameworks platform was developed to realize multi-channel, feedback-controlled program-controlled stimulus output. The proposed software was designed with a user-friendly interface and stimulating/recording switch function, and could dynamically change stimulation programs and switch electrodes during the experiment process. Results The results showed that the software could control the stimulators steadily and generate random stimulation protocols and synchronization control signals according to the user-supplied dynamical parameters, including electrodes, amplitudes, and intervals. In the stimulation sequence, the switching delay between two electrodes was around 600 ms level. Conclusion The software has good compatibility with existing equipment systems. It can achieve multi-channel, real-time, feedback-controlled program-controlled stimulation according to the characteristics and needs of multi-lead neural electrophysiological stimulation researches. It has the functions of dynamically changing the stimulation program and switching electrodes during operation. This software provides tools for the study of the mechanism of network-level neural network feedback loops. Key words: Multi-electrode array; Programmed stimulation; Runtime electrode switching; Neuronal networks; Network response

Chapter 15 - Software Verification and Validation Practice

Valve positioner is the core component of the pneumatic control valve. A new software and hardware design scheme of intelligent valve positioner is presented in this paper. The circuit composition of each part of the intelligent valve positioner is introduced in hardware part. Based on it, a hardware solution to realize HART ‘multi-point’ communication is proposed in this research. In the software design, a novel combined PID control algorithm is proposed to solve the nonlinear problem caused by the friction between the valve stem and the packing during the control process. Simulation results show that the method proposed in this paper is better than traditional PID method and fuzzy PID method. The software and hardware design scheme of the valve positioner proposed in this paper has certain guiding significance for the development of related products.

Power Electronics Building Block (PEBB) concept has been proposed to simplify the conventional design process and reduce engineering efforts. The main idea of PEBB is to standardize the hardware and software design. A PEBB hardware is a power processor which integrates different groups of hardware components such as power semiconductors, sensing measurements and communication interface elements. Different range of power converters can be constructed easily by connecting a number of identical PEBBs in series and/or parallel. However, failure of a PEBB will degrade the reliability level of these converters. To prevent system breakdown, the life span of a PEBB hardware must be estimated so that maintenance works can be planned ahead. Therefore, this paper demonstrates part stress analysis to estimate a useful-life-cycle (Mean Time To Failure) of a well-developed PEBB hardware prototype. This PEBB has been used to construct a small-scaled modular multilevel converter for laboratory testing. Full reliability block diagram analysis and simplification techniques are enclosed.

In order to improve the accuracy of silicon piezoresistance pressure sensor under different temperatures, temperature compensation should be carried out. A temperature compensation system of pressure sensors is presented. The structure, hardware and software design of the system are introduced. In the hardware design, MAX1452 is used as the main compensation unit. A curve fitting algorithm based on cubic B-spline is adopted in the temperature compensation software design. The accuracy and the production efficiency of the sensors are improved. The system features in low cost, high efficiency and high accuracy. And it has great spreading value

The move towards higher levels of abstraction in hardware design begins to blur the difference between hardware and software design. Nevertheless, the attractiveness of a software implementation is still defined by the much smaller abstraction gap between specification and implementation. Whereas, hardware design creates the possibility to exploit parallelism at a very fine level of granularity and thereby achieve tremendous performance gains with a moderate expenditure of hardware. This paper describes the joint design process leading to an ASIC chipset accelerating the execution of rulebased systems. The interaction between the algorithm used for software implementation and the parallel algorithm suited for hardware implementation is examined. An area efficient implementation of the programmable hardware was enabled by an application specific compiler backend. The heuristics applied by the optimising “code” generator are discussed quantitatively.

Through the analysis of specific test requirements, this topic design the overall architecture of the automatic test system. In the hardware design, this topic mainly discusses the hardware circuit design of the interface adapter. In the software design, this topic mainly discusses the secondary package of instrument module driver, the application development of interface adapter driver and test software. Finally, this system have been applied in the field more than once. It turns out that this system is able to test the performance indicators of units of radio, and the test results are accurate, the test efficiency is also high.

This paper introduces the relevant content of LXI bus technology including its developments, classification, and research status of synchronous triggering of LXI bus. Based on the discussion of hardware triggering techniques, a feasible structure of LXI class A instrument is proposed. Its hardware and software design is described in detail. In hardware design, the M-LVDS drivers are adopted to complete the transmission of triggering events and satisfy the specification of LXI class A instruments. Because of the high performance cast ratio, ARM processor is adopted to be the controller of the instrument. The software scheme is also proposed. The instrument software is designed as a Web server. With a browser, users can access LXI instruments through communicating with IVI-COM drivers. The proposed instrument scheme has the advantages of wider coverage, better succession, longer life cycle, lower cost, greater data throughput and so on.

A Hall sensor array system for magnetic field detection and analysis is realized in X-FAB 0.18 μm CMOS technology. Magnetic field detection is attributed to the magnetization of metal coils to metal particles and the sensing characteristics of the Hall sensor array. The system puts forward a complete solution from Hall sensors, analog front-end circuit, analog-to-digital converter (ADC) to microcontroller unit. Using Ansoft Maxwell and COMSOL Multiphysics software for simulation verification, the minimum diameter of magnetic particles that can be detected in the system is 2 μm. The measured signal to noise and distortion ratio, spurious free dynamic range, and effective number of bits of the proposed ADC are 70.61 dB, 90.08 dB, and 11.44-bit, respectively. The microsystem based on STM32 combines hardware and software design, which can effectively adjust the motion parameters and realize the real-time display in the LCD screen of the magnetic field and voltage information. Compared to the prior system, the portability, cost, and efficiency have been considerably improved, which is aimed at the rapid measurement of heavy metal particles such as Fe, Co, and Ni in ambient air and blood.