On static compaction of test sequences for synchronous sequential circuits

Today, VLSI design has progressed to a stage where it needs to incorporate methods of testing circuits. The Automatic Test Pattern Generation (ATPG) is a very attractive method and feasible on almost any combinational and sequential circuit. Currently available automatic test pattern generators (ATPGs) generate test sets that may be excessively long. Because a cost of testing depends on the test length, compaction techniques have been used to reduce that length. The motivation for studying test compaction is twofold. Firstly, by reducing the test sequence length, the memory requirements during the test application and the test application time are reduced. Secondly, the extent of test compaction possible for deterministic test sequences indicates that test pattern generators spend a significant amount of time generating test vectors that are not necessary. The compacted test sequences provide a target for more efficient deterministic test generators. Two types of compaction techniques exist: dynamic and static. The dynamic test sequence compaction performs compaction concurrently with the test generation process and often requires modification of the test generator. The static test sequence compaction is done in a post-processing step to the test generation and is independent of the test generation algorithm and process. In the thesis, a new idea for static compaction of test sequences for synchronous sequential circuits has been proposed. Our new method - SUSEM (Set Up Sequence Elimination Method) uses the circuit state information to eliminate some setup sequences for the target faults and consequently reduce the test sequence length. The technique has been used for the test sequences generated by HITEC test generator. ISCAS89 benchmark circuits were used in our experiments, for some circuits which have a large number of target faults and relatively small number of flip-flops, the very significant compactions have been obtained. The more important is that this method can be used to improve the test generation procedure unlike most static compaction methods which blindly or randomly remove parts of test vectors and cannot be used to improve the test generators.

Short test sequences for synchronous sequential circuits are important in reducing test application time and memory requirements. In addition, dynamic test compaction, where heuristics to generate short test sequences are incorporated into the test generation process, may also reduce test generation time. This is due to the fact that a smaller number of test vectors needs to be generated. We present a dynamic test compaction procedure. The compaction heuristics we use are based on previously proposed static compaction techniques. Conventionally, static compaction is applied as a postprocessing step, after the test sequence has been generated. In the proposed procedure, static compaction techniques are used while the test sequence is being generated, to reduce the need for postprocessing, or static compaction. Compared to other dynamic compaction procedures that generate very short test sequences, the computational overhead involved in the proposed procedure is significantly lower, yet short test sequences are obtained. The proposed techniques can be incorporated into other test generation procedures, to reduce the test lengths they produce.

The problem of test generation for path delay faults in synchronous sequential circuits is addressed. In existing testing methods, a single fast clock cycle is used to activate path delay faults and a fault is said to be detected only if the fault free response is different from the faulty response at a single output and at a specified time unit in the test sequence. We refer to these methods as single fast clock cycle and single observation time testing methods. We show that testable faults may exist, which are untestable using a single fast clock cycle and a single observation time. Such faults are testable when multiple fast clock cycles and/or multiple observation times are used. A test generation procedure is given that uses multiple fast clock cycles and multiple observation times. Experimental results are presented on MCNC synthesis benchmarks to demonstrate the effectiveness of the proposed strategy in increasing the fault coverage and reducing the test length.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

We propose several compaction procedures for synchronous sequential circuits based on test vector restoration. Under a vector restoration procedure, all or most of the test vectors are first omitted from the test sequence. Test vectors are then restored one at a time or in subsequences only as necessary to restore the fault coverage of the original sequence. Techniques to speed-up the restoration process are investigated. These include limiting the test vectors initially omitted from the test sequence, consideration of several faults in parallel during restoration, and the use of a parallel fault simulator.

We describe a new approach to test generation for stuck-at faults in synchronous sequential circuits. Under this approach, the input vectors comprising the test sequence are fixed in advance. The process of generating the test sequence consists of ordering the precomputed input vectors such that the resulting test sequence has as high a fault coverage as possible. The advantage of this approach is that its computational complexity is limited by limiting the search space to a given set of input vectors and a given test sequence length. We describe a specific implementation of this approach. Experimental results demonstrate that restricting the search space to a fixed number of precomputed input vectors is sufficient for achieving the highest known fault coverage, or a fault coverage close to it, for benchmark circuits.

Test sequences for acyclic sequential circuits can be generated by using a time expansion model. In this paper, static and dynamic test sequence compaction techniques are proposed in which the test sequence generated by the time expansion model has two characteristics: (1) The test sequence length is constant, and (2) The location of an undefined value (X) for all primary inputs can be determined independently of test generation faults. First, a static test sequence compaction method is proposed that uses a template which is independent of the value of the test sequence. Then a dynamic test sequence compaction method is presented using reverse transform fault simulation, performing fault simulation for the time expansion model of the test pattern in which the test sequence after compaction is reverse‐transformed. As a result of application of the proposed method to acyclic sequential circuits made by using partial scan design, the test sequence length was reduced by 19 to 34%. © 2002 Wiley Periodicals, Inc. Syst Comp Jpn, 33(10): 105–115, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.1162

We propose a procedure for generating test sequences for diagnosis of synchronous sequential circuits based on stuck at faults. In this procedure, we avoid the conventional fault-oriented test generation process by observing that a sequence to distinguish two faults can be obtained from a sequence T that detects both of the faults (such as a test sequence for fault detection) by changing T so as to "undetect" one of the faults, or change the time units or outputs where the fault is detected. To achieve this goal, the proposed procedure eliminates parts of T so as to render some of the faults undetected, or change their detection times or outputs. In the case where faults become undetected by the modified sequence, the detected faults are distinguished from the faults left undetected by the modified sequence based on pass/fall information. A pass/fall dictionary based on modified test sequences is proposed for this case. Alternatively, a standard dictionary can be used, and the proposed procedure can be used to change the time units or outputs where faults are detected in order to distinguish them. We present experimental results to demonstrate the levels of resolution that can be obtained by the proposed procedure with the proposed pass/fail dictionary, and the number of sequences required for this purpose.

The restoration-based compaction procedures are the most computationally efficient static compaction procedures that reduce the length of a test sequence for a synchronous sequential circuit without reducing the fault coverage. We study one of the important components of the restoration-based compaction process, the initial omission process. This process selects test vectors that will be omitted from the test sequence initially, to start the restoration process. We also propose a specific procedure for the initial omission process. Experimental results for a variety of circuits and test sequences demonstrate that this procedure has a significant effect on the compacted test sequence length. Intuitively, the new procedure postpones the point at which the compaction procedure saturates, thus allowing smaller test lengths to be obtained before saturation is reached. The importance of continuing to explore this problem is related to the fact that static compaction procedures for synchronous sequential circuits are important for scan circuits as well.

Full scan design renders every combinationally irredundant fault in a synchronous sequential circuit testable. In this paper, we derive a similar result applicable to design-for-testability techniques that only controls the initial state of the circuit in order to improve its testability. Examples of such techniques are parallel load, reset, and scan when it is used only to set the state of the circuit. We show that if the initial state can be set arbitrarily, a test sequence can be generated for every irredundant fault, i.e., for every fault that is not sequentially or combinationally redundant. Thus, the ability to control the state of the circuit is sufficient for detecting every irredundant fault and observability of the circuit state is not necessary for this purpose. When considering scan, this result implies that scan-out can be used to control the test length and test generation time, but it is not necessary for detecting irredundant faults. We also show that, of all the states of the circuit, it is sufficient to consider as possible initial states (or controllable states) only the states extracted from a complete combinational test set. We demonstrate the use of these observations by presenting experimental results of two applications. In the first application, initial states are selected out of a combinational test set to facilitate deterministic test generation for irredundant faults. In the second application, the ability to set the initial state is used to increase the effectiveness of built-in self-test.

&lt;p&gt;Test generation procedures for large VLSI designs are required to achieve close to 100% fault coverage using a small number of tests. They also must accommodate on-chip test compression circuits which are widely used in modern designs. To obtain test sets with small sizes one could use extra hardware such as test points or use software techniques. An important aspects impacting test generation is the number of specified positions, which facilitate the encoding of test cubes when using test compression logic. Fortuitous detection or generation of tests such that they facilitate detection of yet not targeted faults, is also an important goal for test generation procedures.&lt;/p&gt; &lt;p&gt;At first, we consider the generation of compact test sets for designs using on-chip test compression logic. We introduce two new measures to guide automatic test generation procedures (ATPGs) to balance between these two contradictory requirements of fortuitous detection and number of specifications. One of the new measures is meant to facilitate detection of yet undetected faults, and the value of the measures is periodically updated. The second measure reduces the number of specified positions, which is crucial when using high compression. Additionally, we introduce a way to randomly choose between the two measures.&lt;/p&gt; &lt;p&gt;We also propose an ATPG methodology tailored for BIST ready designs with X-bounding logic and test points. X-bounding and test points used to have a significant impact on test data compression by reducing the number of specified positions. We propose a new ATPG guidance mechanism that balances between reduced specifications in BIST ready designs, and also facilitates detection of undetected faults. We also found that compact test generation for BIST ready designs is influenced by the order in which faults are targeted, and we proposed a new fault ordering technique based on fault location in a FFR. Transition faults are difficult to test and often result in longer test lengths, we propose a new fault ordering technique based on test enumeration, this ordering technique and a new guidance approach was also proposed for transition faults. Test set sizes were reduced significantly for both stuck-at and transition fault models.&lt;/p&gt; &lt;p&gt;In addition to reducing data volume, test time, and test pin counts, the test compression schemes have been used successfully to limit test power dissipation. Indisputably, toggling of scan cells in scan chains that are universally used to facilitate testing of industrial designs can consume much more power than a circuit is rated for. Balancing test set sizes against the power consumption in a given design is therefore a challenge. We propose a new Design for Test (DFT) scheme that deploys an on-chip power-aware test data decompressor, the corresponding test cube encoding method, and a compression-constrained ATPG that allows loading scan chains with patterns having low transition counts, while encoding a significant number of specified bits produced&lt;/p&gt; &lt;p&gt;by ATPG in a compression-friendly manner. Moreover, the new scheme avoids periods of elevated toggling in scan chains and reduces scan unload switching activity due to unique test stimuli produced by the new technique, leading to a significantly reduced power envelope for the entire circuit under test.&lt;/p&gt;

A test generation procedure for synchronous sequential circuits is proposed, that is based on the multiple observation times approach, and uses homing sequences, instead of conventionally used synchronizing sequences, to initialize the circuit. A procedure for computing homing sequences in sequential circuits, for which a state-table description is too large to be practical, is described, and experimental results are presented to demonstrate the effectiveness of the proposed test generation procedure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Test generation for synchronous sequential circuits can be facilitated by decomposing the circuit into a cycle free interconnection of submachines, such that all feedback loops are included within the submachines. In this work, we describe a test generation procedure that takes advantage of cycle free circuit decomposition. The paper focuses on one of the subproblems of the test generation problem, the output sequence justification problem. We propose a solution to this problem and show how it can be incorporated into a test generation procedure.

We propose a new technique for static compaction of test sequences. Our method is based on two key ideas: (1) overlapped vector restoration, and (2) identification, pruning, and re-ordering of segments. Overlapped restoration provides a significant computational advantage for large circuits. Segments partition the compaction problem into sub-problems. Segments are identified, dynamically pruned and re-ordered to achieve further compaction and speed up. When compared to the fastest method proposed by I. Pomeranz and S.M. Reddy (1997), our method was 5 to 30 times faster on ISCAS circuits and 20 to 50 times faster on large, industrial designs. The new algorithm was able to successfully process large industrial designs that could not be handled by earlier techniques in 2 CPU days.

A method for generating tests for gate-level stuck-at faults in sequential machines is given, which is applicable when a state-table description of the machine under test is either given or extractable from the given description. A test generation procedure for faults in the state table is first described. The test generation procedure is polynomial in the size of the state table, and is complete and accurate in the following sense. For every given state-table fault, the procedure provides either a minimum-length test, or a proof that the fault is undetectable. This test generation procedure is used for generating complete test sets for stuck-at faults in a gate level implementation of the machine, by translating stuck-at faults in the gate-level implementation into faults in the state table. The translation includes modeling and extraction. Modeling consists of a simple method to select a small subset of state-table faults such that a test set for these faults yields very high coverage of stuck-at faults in the actual implementation. Extraction consists of accurate translation of stuck-at faults in the implementation into equivalent state-table faults, and can be used to derive tests for stuck-at faults which are not detected by the test set for the modeled faults. Based on the test generation algorithm developed and the modeling and extraction of stuck-at faults to translate them into state-table faults, a method to achieve 100% fault-efficiency for stuck-at faults is proposed, and experimental results for stuck-at faults are presented. Short test sequences are shown to be obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Due to the complexity of test generation for stuck-at-faults in synchronous sequential circuits and the permanently increasing problem-size, algorithms solving this problem cannot work with acceptable CPU-time, even on computer systems with very high performance. Relating to this context this paper presents a new testability analysis guiding algorithms for sequential test generation. This testability analysis consists of two separated parts: First, a new technique for the detection of untestable stuck-at-faults; second, heuristics used to guide the decision process in test generation algorithms. Experimental results of sequential benchmark circuits allow us to conclude that our testability analysis provides less CPU-time for sequential test generation than other well-known testability analysis tools. >