Optical backplane for board-to-board interconnection based on a glass panel gradient-index multimode waveguide technology

Investigation of environmental reliability of optical polymer waveguides embedded on printed circuit boards

Optical technologies have received large interest in recent years for use in board-level interconnects. Polymer multimode waveguides in particular, constitute a promising technology for high-capacity optical backplanes as they can be cost-effectively integrated onto conventional printed circuit boards (PCBs). This paper presents the first optical backplane demonstrator based on the use of PCB-integrated polymer multimode waveguides and a regenerative shared bus architecture. The backplane demonstrator is formed with commercially-available low-cost electronic and photonic components onto conventional FR4 substrates and comprises two opto-electronic (OE) bus modules interconnected via a prototype regenerator unit. The system enables interconnection between the connected cards over four optical channels, each operating at 10 Gb/s. Bus extension is achieved by cascading OE bus modules via 3R regenerator units, overcoming therefore the inherent limitation of optical bus topologies in the maximum number of cards that can be connected to the bus. Details of the design, fabrication, and assembly of the different parts of this optical bus backplane are presented and related optical and data transmission characterisation studies are reported. The optical layer of the OE bus modules comprises a four-channel three-card waveguide layout that is compatible with VCSEL/PD arrays and ribbon fibres. All on-board optical paths exhibit insertion losses below 13 dB and intra-channel crosstalk lower than -29 dB. The robustness of the signal distribution from the bus inputs to all respective bus output ports in the presence of input misalignment is demonstrated, while 1 dB input alignment tolerances of approximately ±10 μm are obtained. The electrical layer of the OE bus modules comprises the essential driving circuitry for 1×4 VCSEL and PD arrays and the corresponding control and power regulation circuits. The interface between the optical and electrical layers of the bus modules is achieved with simple OE connectors that enable end-fired optical coupling into and out of the on-board polymer waveguides. The backplane demonstrator achieves error-free (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) 10 Gb/s data transmission over each optical channel, enabling therefore, an aggregate interconnection capacity of 40 Gb/s between any connected cards.

A new-generation interconnect for optical backplane systems based on printed circuits board is presented for transmitting data via integrated multimode polymer optical waveguides both on electro-optical transmitter/receiver processing boards and on optical backplane board. Different developments concerning this system such as optical waveguide technology, transmitter/receiver module activities, and optical interconnect/coupling concepts are discussed.

Optical waveguides have shown promising results for use within printed circuit boards. These optical waveguides have higher bandwidth than traditional copper transmission systems and are immune to electromagnetic interference. Design parameters for these optical waveguides are needed to ensure an optimal link budget. Modeling and simulation methods are used to determine the optimal design parameters needed in designing the waveguides. As a result, optical structures necessary for incorporating optical waveguides into printed circuit boards are designed and optimized. Embedded siloxane polymer waveguides are investigated for their use in optical printed circuit boards. This material was chosen because it has low absorption, high temperature stability, and can be deposited using common processing techniques. Two sizes of waveguides are investigated, 50 $unit{mu m}$ multimode and 4 - 9 $unit{mu m}$ single mode waveguides. A beam propagation method is developed for simulating the multimode and single mode waveguide parameters. The attenuation of simulated multimode waveguides are able to match the attenuation of fabricated waveguides with a root mean square error of 0.192 dB. Using the same process as the multimode waveguides, parameters needed to ensure a low link loss are found for single mode waveguides including maximum size, minimum cladding thickness, minimum waveguide separation, and minimum bend radius. To couple light out-of-plane to a transmitter or receiver, a structure such as a vertical interconnect assembly (VIA) is required. For multimode waveguides the optimal placement of a total internal reflection mirror can be found without prior knowledge of the waveguide length. The optimal placement is found to be either 60 µm or 150 µm away from the end of the waveguide depending on which metric a designer wants to optimize the average output power, the output power variance, or the maximum possible power loss. For single mode waveguides a volume grating coupler is designed to couple light from a silicon waveguide to a polymer single mode waveguide. A focusing grating coupler is compared to a perpendicular grating coupler that is focused by a micro-molded lens. The focusing grating coupler had an optical loss of over -14 dB, while the grating coupler with a lens had an optical loss of -6.26 dB.

Parallel optical interconnects on-board level requires low propagation loss in wavelength range between 850 and 1550 nm to be compatible with datacom and telecom optical engines. For highest integration density tight waveguide bends and a scalable number of optical layers should be manufacturable for 2D interfaces to optical fiber array connectors and photonic assembly I/O's. We developed a glass waveguide panel process for double-sided processing of commercial available display glass by applying a two-step thermal ion-exchange process for low-loss multi-mode graded-index waveguides. Multiple glass waveguide panels can be embedded between electrical layers. The generic concept enables fabrication of high-density integration (HDI) electro-optical circuit boards (EOCB) with high number of optical and electrical layers. Waveguides with high NA of 0.3 for low bend losses could be achieved in glass with propagation loss of 0.05 dB/cm for all key wavelengths. Four of those glass waveguide panels were embedded in an EOCB demonstrator with size of 280 x 233 mm² providing eight optical layers with 96 channels in an area of 2.8 x 1.5 mm². To the best of our knowledge it's the highest number of layers that has ever been demonstrated for an EOCB.

The system performance of data- and telecommunication equipment must keep up with the increasing network speed. Optical interconnections technology is a promising alternative for high-throughput systems. We demonstrate the optical backplane system using a waveguide-embedded optical backplane and two processing boards. The transmitter and receiver modules were prepared for optical printed circuit boards (PCBs), which consists of the metal optical bench, the driver chips, vertical-cavity surface-emitting lasers (VCSELs), photodiodes, and a tapered polymeric waveguide. We report high-speed transmission of 27–1 pseudorandom bit sequence (PRBS) nonreturn to zero (NRZ) data up to 10 Gbits/s through the optical backplane system. The results demonstrate that the optical backplane system can be practical and valuable for the future high-throughput systems by using metal optical bench and precisely machined optical plug-adaptor structure to achieve stable board-to-board interconnection.

The research object in the work is the printed circuit boards (PCB) Production technological process using the additive technology of photopolymer 3D printing. The existing problem is that the manufacturing process of single-sided and double-sided PCBs, simple in technology, from the third to the fifth accuracy class, requires the use of a large amount of consumables and technological equipment. In turn, this affects the cost of the product. The research subject is models and methods for manufacturing PCB using photopolymer 3D printing. In order to reduce the cost of materials: film or aerosol photoresist, as well as reduce the number of technological operations, applying photoresist and for the manufacture of PCBs stencils, it is proposed to use photopolymer 3D printing technologies for the manufacture of PCBs. The paper analyzes the costs of Plexiwire Resin Basic Orange Transparen photopolymer resin for the manufacture of single-sided PCBs and calculates the cost of the consumable (resin) compared to the costs of dry film photoresist. 60 % cost of consumables (photopolymer resin) compared to dry film photoresist for making single-sided PCBs. The work is aimed at determining the dependence of the geometric dimensions of the PСВs topology and the consumption of photopolymer resin on the technological parameters of photopolymer exposure. A regression correlation model of the dependence of resin consumption on exposure parameters has been developed and correlation coefficients have been calculated. It has been established that with an increase in the exposure time of the photopolymer resin, the consumption of the photopolymer resin increases and the deviation of the geometric dimensions of the PCBs topology increases, which in turn negatively affects the quality of the product. Therefore, using the obtained regression model, it is possible to calculate the influence of parameters on the PCB topology and reduce the deviation of conductor sizes and resin consumption.

A high-density packaging approach has been developed that uses hermetic ceramic packages made with thick-film techniques. The overall packaging density, at the printed circuit (PC) board level, is comparable to or better than that achieved with some multichip packaging approaches. Low-cost thick-film ceramic packages are produced with no hard tooling from multiple sources. Chips are packaged, burned in, and tested in these packages with standard processes and production lines. The ceramic packages are then cut down to a smaller size by laser scribing and are mounted on printed circuit boards. The packages are then interconnected to the board by automatic gold-to-gold wire bonding. The author describes practical aspects of this packaging approach with respect to the design and fabrication of the thick-film ceramic packages, chip packaging and test using these packages, PC board design and fabrication, and PC board assembly. The issues of procurement costs, design, fabrication cycle times, parts screening, packaging density, rework, electrical considerations, thermal performance, process maturity, and reliability are also discussed. >

Shadow moire technique is already well-established as a technique for evaluating component warpage. Improvements to the metrology have increased its usefulness for evaluating various board-level manufacturing technologies. This experiment used the technique for two key board-level applications: i) Bare printed circuit board (PCB) warpage during the lead-free reflow: PCB warpage is becoming more significant due to the higher temperature required for lead-free reflow. This work used shadow moire dynamic reflow simulation to explore the effect of three variables - board thickness, glass transition temperature, and vendors - on board warpage. The test data showed clearly that board thickness is the most significant variable; ii) Assembled board warpage under mechanical preload from thermal solutions and under thermal cycling: One of the heatsink design approaches for desktop motherboards is to apply a preload to the CPU area of a motherboard in order to ensure thermal performance. This approach requires a more careful control of the preload. Board warpage is significant and is identified as a good metrology for preload estimation. Motherboards under three different preloads in the CPU area were measured. Both the global board warpage and the local board warpage around the CPU area were measured for preload correlations. The measured board warpage was correlated to the board preload successfully. In addition to these two issues, other examples are discussed briefly to demonstrate the capability of the board level shadow moire technique. The work proved that the metrology has become an indispensable thermal-mechanical analysis for manufacturing technology evolutions.

The rapid development of information and communication technologies has driven the rapid growth of data traffic and the large requirement of high-speed optical transceiver modules. Usually, optical subassemblies through flexible printed circuit boards (PCBs) connect with the hard PCBs to compose as optical transceiver modules. Because of the impedance mismatch of connection between flexible PCB and hard PCB, the operation bandwidth of the module can be limited. In this paper, the design of connection between flexible PCB and hard PCB in optical subassembly modules will be investigated for increasing the operation speed of the module. First, the transmission bandwidth of flexible PCB is analyzed. High-frequency performances of three transmission line structures, micro-strip line, grounded coplanar waveguide, and top ground micro-strip line, are investigated in flexible PCB. High-frequency performances of flexible PCB with different bending types are also investigated. The flexible PCB has been verified to be suitable to use in 25 Gb/s applications. Next, the high-speed transmission performance is analyzed through the connection between flexible PCB and hard PCB, because the impedance mismatch usually occurs at the connection. The ground pads are added near the signal line of flexible PCB, and the ground pads are connected to the ground layer in PCB through ground vias. The anti-pad in hard PCB is added under the signal solder pad. The dip of S21 response can be eliminated by the optimized ground pad. The impedance mismatch can be reduced by the optimized anti-pad, the impedance increases from 40-Ω to 49-Ω at the connection between flexible PCB and hard PCB, and the transmission bandwidth can increase from 16.5 GHz to 23.5 GHz. TO-46 header is a common and low-cost packaging solution for DFB laser and photodiodes. The connection between flexible PCB and TO-46 header is also investigated. While the connection has a gap, the dip of frequency response will occur at lower frequency. While the connection is very close, the bandwidth can be larger than 25 GHz. The flexible PCB, hard PCB, and TO-46 header are combined together, and the 23 GHz transmission bandwidth can be obtained. The 25 Gb/s transmission eye diagram is also measured, and the eye height, rise time, fall time, and Q-factor are 268.14 mV, 13.78 ps, 13.56 ps, and 8.76, respectively. The combined flexible PCB, hard PCB, and TO-46 header are verified to be suitable to apply in 25 Gb/s optical subassembly modules, and will be able to be used in 100G Ethernet.

An innovative approach is described for diagnosing faults in printed circuit boards (PCB) and PCB components through the detection, analysis, and localization of electrical field changes that occur within and around the PCB. This method utilizes electromagnetic emissions (EME) originating from the PCB to determine circuit health. EME from rapidly changing voltages and currents within high-speed logic and other circuits have traditionally been seen as a problematic source of interference that must be eliminated to as great an extent as possible. However, changes within these emissions can be a highly significant indicator that a failure has occurred within a PCB component as well as within adjacent circuit card paths of the board itself. Further, the hardware and software requirements needed to capture and analyze these emissions are relatively simple in comparison to todaypsilas highly complex automatic test equipment. This unique approach involves analyzing electromagnetic emission signatures through automated means, and ascribing failures to the circuit board as a whole, as well as to the individual circuit board components.

"Electronic manufacturing is currently one of the fastest growing industrial areas. This is due to the rapid advances in the computer and telecommunications sectors. Due to these advances, new surface mount devices have been developed to achieve greater miniaturisation at lower costs. As a result, a new surface mount technology has been developed to mount these devices onto printed circuit boards. However, problems exist with aspects of this process, principally open solder joints which result from circuit board warpage. The aim of this thesis is to undertake a) both an experimental and theoretical investigation of the reflow solder process and b) to develop thermal and structural models to analyse circuit board warpage. This research should aid manufacturing engineers in understanding the influence of the solder reflow process parameters on board warpage. Extensive experimental testing of the circuit board materials during the process is also presented. The thermal model detailed in this thesis simulates a) forced convective heat transfer through air impingement to the boards and b) the three dimensional temperature distribution within a composite laminate. The thermal model predicts the temperature distribution within a populated laminated composite circuit board to within 3% when compared to experimental data. The experimental results show that the convective heat transfer coefficient is primarily dependant on Reynolds number, and also the orifice to plate distance and orifice diameter. It was found that at high Reynolds number, the heat transfer coefficient increases significantly at low orifice to board distance. This heat transfer rate has to be balanced against the maximum speed of the air to prevent the components been blown off the boards. The 5mm diameter orifice provides the optimum balance between air speed and heat transfer rate. The structural model simulates the influence of a) board support, b) reflow temperature profile, c) components on the board and d) board layup on circuit board deformation. The experimental appraisal and model predictions show that the warpage of the printed circuit boards is dependant on a) support of the board during the process, b) symmetry of the board layup, c) coefficients of thermal expansion of the board materials, d) temperature distribution in the boards i.e. symmetric or nonsymmetric about board centre and e) temperature applied to the board. This research proves that if adequate support is applied to the boards during the reflow soldering process then, the warpage of the printed circuit boards may be kept within acceptable margins. Board warpage exists in current printed circuit boards because a) the boards cannot be manufactured truly symmetric in layup and b) Non-uniform temperature distributions are present in the board during the solder reflow process which leads to non-uniform expansion of the constituent laminate layers due to their varying coefficients of thermal expansion."

Electronic package manufacturers publish thermal characteristics of components, which are measured using standard tests, measuring a thermal resistance value for a single component on a standard test printed circuit board (PCB). This limits the applicability of the characterization, as it does not show what aerodynamic or thermal interaction each package will have in a real system. This paper presents a new board-level electronics system test vehicle consisting of an array of ball grid components on three different effective thermal conductivity multi-layer PCB’s. Aerodynamic and thermal measurements are presented. It appears that PCB’s populated with low profile electronic packages behave like flat plates, leading to the proposition that component temperatures can be calculated using flat plate predictions. It is shown how both the airflow and the board conductivity can have a critical effect on the junction temperature, and a simple design rule is suggested, in terms of influence factors, to take account of these effects. These will lead to better estimates of electronic system reliability in the early part of the design cycle.

PCB drop test lifetime assessment based on simulations and cyclic bend tests

The exponential increase of Internet traffic due to cloud computing and other emerging web applications has created the need for more powerful data centres. These warehouse-scale data centres consist of thousands of racks interconnected with commodity switches and consume vast amount of energy. To face the requirements of the future data centres, new interconnection schemes have to be adopted to provide high throughput and reduced power consumption. Several optical interconnects for future data centre networks have recently appeared that provide high throughput, low latency and reduced power consumption. This paper discusses the need for a shift of the data centres networks to the optical domain to reduce the power consumption and meet the bandwidth requirements. Additionally, this paper presents some indicative optical interconnects for high performance data centres that have appeared recently in the research literature. Finally, it presents a qualitative categorization and comparison of these schemes based on their main features such as performance, connectivity and scalability.