Optimal Control of Transient Enhanced Diffusion

According to the recently released 1999 National Technology Roadmap for Semiconductors, the SID extension junction will be in the range of a few tens of nanometers for the up coming 180 nm and 130 nm nodes. Although the junctions have to become shallower, a decreasing sheet resistance is required. The formation of ultra-shallow junctions is mainly influenced by three important parameters, these are: dose and energy control during ion implantation, a controlled gaseous ambient during RTA (rapid thermal anneal), and a controlled and reproducible thermal budget during RTA. The requirements for production tools have become progressively more stringent, but the crystal off-orientation of the wafer surface condition as an issue in reproducible USJ formation has been neglected. In Si wafer production, the exact [100] orientation of the wafer surface is determined by the ingot sawing accuracy and typically done with a tolerance of +0.1/spl deg/. Prior to this experiment, however, the influence of such a variance in the wafer off-orientations on the junction characteristics had not been investigated. For our experiments repeatable "off-axis" from [100] sliced 200 mm silicon wafers were implanted with /sup 11/B/sup +/, /sup 75/As/sup +/ or /sup 31/P/sup +/ at a tilt and twist angle of 0/spl deg/ to investigate the effects on junction depth and sheet resistance. The acceleration voltage varied between 500 eV (/sup 11/B/sup +/) and 5 keV (/sup 75/As/sup +/). The off-orientation varied between exact 0/spl deg/ and the channeling-reduction-angle for boron of 7.00 (e.g. 0.35/spl deg/, 1.0/spl deg/, 4.0/spl deg/). Species depending data of as-implanted distributions as well as soak time (1050/spl deg/C 10 s) and flash annealed (with a ramp rate of 350 Ws) wafers are presented and the influences of the off-oriented sliced wafers on junction depth and sheet resistance are discussed.

We have investigated the limits on sheet resistance, junction depth and abruptness using ultra low energy As implants and RTA annealing. We report on anomalous diffusion of 1 keV arsenic implants where the same RTA anneal can result in a deeper junction compared to a 5 keV implant of similar dose. A range of anneal times and temperatures in an RTA from 1020C to 1175C, including spike anneals, have been studied. The effect of junction abruptness in reducing the external resistance of the S/D extension for these 5 and 1 keV As implants has been investigated. We show that because of a trade off between junction depth and sheet resistance limits, 1 keV As implants and RTA anneals cannot meet the technology roadmap requirements beyond 2005, though the junction abruptness will meet the requirements till 2011.

The fabrication of advanced CMOS devices calls for production worthy doping solutions to address requirements for increasingly shallow and abrupt junctions, while maintaining high dopant activation to meet series resistance requirements. Plasma Doping (PLAD), which has already been adopted in high volume manufacturing in the ultra high dose, low energy regime for advanced DRAM technology nodes, is now being investigated for source drain extension (SDE) implants, where precise and repeatable dopant placement is critical for maintaining control over device parameters. In this article, we investigate the process performance of SDE implants carried out in a VIISta® PLAD system using p‐ type dopant precursors. Key metrics, such as junction depth, profile abruptness and sheet resistance are reported for as‐implanted junctions, as well as samples processed with low thermal budget anneal techniques. Device performance data demonstrating the feasibility of the approach are presented. The advanced control features ...

Post-annealing effects on the shallow-junction characteristics caused by high-fluence 77 keV BSi molecular ion implantations at room and liquid nitrogen temperatures

Ultra-shallow junction layers are required for deep submicron CMOS and quantum devices. Low-temperature (320 °C) molecular-beam epitaxy was used to form highly conductive, ultra-shallow layers in silicon using boron delta doping. The as-grown junction depths, determined with secondary ion mass spectrometry, ranged from 7 nm to 18 nm. A minimum resistivity of 3 x 10 -4 Ω-cm was obtained when the delta-doped layers were spaced 2.5 nm apart. The sheet resistances of the epitaxial layers, plotted as a function of junction depth, followed the theoretical curve for a box-doped layer having a boron doping concentration equal to the solid solubility limit, 6 x 10 20 /cm 3 . Minimal change was detected in either the atomic profiles or the resistivity after a 10 s rapid thermal anneal (RTA) or a 10 min furnace anneal (FA) up to 700 °C. The sheet resistances of the as-grown shallow junctions are substantially less than those obtained by ion implantation. Only after the 800 °C FA did the MBE-grown layers degrade to have as large a sheet resistance as the best ion implanted layers.

New self‐aligned silicided junctions have been developed by rapid thermal annealing in vacuum for applications to VLSI technology. These silicided junctions were investigated in regard to sheet resistance, junction depth, junction leakage current, and impurity depth profiles. After Ti film (35 nm) was deposited by dc magnetron sputtering, Si+ was implanted for interface mixing and rapid thermal annealing (RTA) in vacuum (∼10−1 Pa) were performed in temperature range of 550°–750°C. In these temperature ranges, the lateral growth of titanium silicide was prevented. After Si+ implantation through the titanium silicide layer to amorphize the Si substrate, As+ and B+ ions were implanted for n+/p junction, and p+/n junction, respectively. Finally furnace annealing (900°C, 30 min) was performed with a cap CVD oxide. We have successfully fabricated the silicided junctions with the junction depth of 0.12 μm, and the leakage current of (at reverse bias of 5.0V) for n+/p junction and of 0.14 μm, and of for p+/n junction.

ABSTRACTThe main challenges for PMOS ultra shallow junction formation remain the transient enhanced diffusion (TED) and the solid solubility limit of boron in silicon. It has been demonstrated that low energy boron implantation and spike annealing are key in meeting the 90 nm technology node ITRS requirements. To meet the 65 nm technology requirements many studies have used fluorine co-implantation with boron and Si+ or Ge+ pre-amorphization (PAI) and spike annealing. Although using BF+2 can be attractive for its high throughput, self-amorphization and the presence of fluorine, many studies have shown that for the fluorine to successfully reduce TED its energy needs to be well optimized with respect to the boron's, therefore BF+2 does not present the right fluorine/boron energy ratio for the optimum junction formation. In this work we optimize the fluorine energy when a deep or shallow PAI is used. We also demonstrate that the fluorine dose needs to be carefully optimized otherwise a reverse effect can be observed. We will also show that the optimized junction depends less on the Ge+ energies between 2 keV and 20 keV and when HF etch is implemented after Ge+ PAI, improvements in both the junction depth and the sheet resistance are observed.

Systematic experimental studies on phosphorus diffusion from phosphosilicate glass into the p-type bulk Si (100) substrate with different capping barrier layer thicknesses have been conducted. In both 2- and 5-nm phosphosilicate glass conditions, a thicker SiO2 cap showed a lower sheet resistance and a higher retained phosphorus dose in the Si substrate after 1050 °C 4 s rapid thermal annealing as drive-in annealing. However, the sheet resistance of 2-nm phosphosilicate glass with a 10-nm SiO2 cap was lower than that of 5-nm phosphosilicate glass with a 3-nm SiO2 cap due to a higher retained phosphorus dose in the Si substrate. For a higher retained phosphorus dose in the Si substrate using fixed total thickness, 2-nm phosphosilicate glass with 6-nm SiO2 cap is better than 5-nm phosphosilicate glass with 3-nm SiO2 cap since prevention of phosphorus out-diffusion during the drive-in annealing is more important than the total phosphorus dose in phosphosilicate glass. Next, SiO2 cap thickness on 2-nm phosphosilicate glass was split to understand the role of the SiO2 capping layer in detail for scaled devices. 3-nm SiO2 cap could not prevent out-diffusion during the drive-in annealing, and it showed much higher sheet resistance and lower retained phosphorus dose in the Si substrate. The highest retained phosphorus dose in the Si substrate was observed for 6-nm SiO2 cap and resulted in 1.8 × 1014 atoms/cm2 retained phosphorus dose with 96% activation level after 1050 °C 4 s rapid thermal annealing. Thicker SiO2 caps than 6 nm were not beneficial since 10-nm SiO2 cap showed a higher sheet resistance value as well as lower phosphorus activation level (82%) compared to 6-nm SiO2 cap even though both the process conditions showed same phosphorus profiles after the drive-in annealing. That sheet resistance increase with 10-nm SiO2 cap could be caused by heterogeneous surface formation on the Si substrate with a prolonged SiO2 atomic layer deposition process.

This paper discusses the diffusion of As, P, and B in amorphous and polycrystalline silicon-on-single-crystal silicon systems during rapid thermal annealing and furnace annealing. It is found that the changes of microstructure during annealing play a major role in determining the diffusion profiles in the substrate as well as in the polycrystalline silicon layer. For As or P doping, a drive-in diffusion results in a much larger grain microstructure for as-deposited amorphous silicon than for as-deposited polycrystalline silicon, which leads to the formation of shallower junctions in the substrate for the first case. For B doping, there is little difference in the final microstructure and junction depth between the two cases. At high anneal temperatures, the native interfacial oxide breaks up, causing epitaxial realignment of the polycrystalline silicon film and subsequent enhanced diffusion in the substrate.

In this paper, the authors investigate the simultaneous processing of the emitter junction and the emitter surface passivation by rapid thermal annealing (RTA) from a doped spin-on glass (SOG). Test structures and solar cells of different emitter profiles and surface concentrations were made by diluting two different doped spin-on glass liquids with methanol. By this procedure, oxide thickness and doping can be controlled. RTA was performed in an argon atmosphere in the temperature range of 850/spl deg/C-1000/spl deg/C for 5-60 sec. The results show that emitter surface doping concentration between 1*10/sup 19/ cm/sup -3/ and 3*10/sup 20/ cm/sup -3/ and junction depth from 0.1 /spl mu/m could be obtained. Sheet resistances lower than 150 /spl Omega///spl square/ could be easily reached. External quantum efficiency measurements from solar cells, made from CZ and FZ p-type silicon wafers, demonstrate the passivation effect of the remaining SOG-film. The highest efficiency obtained with this ohmic back contacted cells, which had an oxide thickness of about 70 nm, are 12.8%.

A systematic and general method of computing ac and dc characteristics of double-diffused junction transistors using major process parameters such as dimensions of the device, surface concentration, junction depth, diffusion time, temperature, and diffusion coefficient as a function of temperature and impurity concentration is described. These parameters can be checked during the process and, therefore, can aid the process control problem by predicting the expected values of junction depth and sheet resistivity. If the specified control parameters are met during the fabrication, the ac and dc characteristics of the device will be realized. The time and/or frequency response of a circuit can be computed using the ac and dc characteristics of the diffused devices of the circuit on the basis of a distributed or an equivalent lumped model. The measurement of important ac parameters on the basis of these models has also been simulated on the computer, thus aiding the characterization problem of the device in the integrated circuit environment. Also, the switching speed of a loaded logic net can be computed and optimized by trading off interacting parameters and relating them back to the original diffusion process parameters and dimensions of the components. Finally, experimental verification of the computed results has been accomplished and found to be satisfactory.

A systematic and general method of computing ac and dc characteristics of double-diffused junction transistors is described using major process parameters such as: dimensions of the device, surface concentration, junction depth, diffusion time, temperature, and diffusion coefficient as a function of temperature and impurity concentration. These parameters can be checked during the process and, therefore, can aid the process control problem by predicting the expected values of junction depth and sheet resistivity. If the specified control parameters are met during the fabrication, the ac and dc characteristics of the device will be realized. The time and/or frequency response of a circuit can be computed using the ac and dc characteristics of the diffused devices of the circuit on the basis of a distributed or an equivalent lumped model. The measurement of important ac parameters on the basis of these models has also been simulated on the computer, thus aiding the characterization problem of the device in the integrated circuit environment. Also, the switching speed of a loaded logic net can be computed and optimized by trading off interacting parameters and relating them back to the original diffusion process parameters and dimensions of the components. Finally, experimental verification of the computed results has been accomplished and found to be satisfactory.

In this paper, for the first time, we report the characteristics of sub-50 nm pMOSFETs using a laser thermal process (LTP) and the technique for enhancing their drive current. For the process optimization required for the technologies of sub-50 nm MOSFETs, we investigated the issues of LTP and cleared them up. S/D-extension (SDE)-junction depth, overlap and sheet resistance were controlled by pre-amorphization ion implantation (I/I) energies, and the first two parameters could be thus controlled regardless of dopant dose. This enabled us to design highly activated and abrupt box-like dopant profiles without inducing any short channel deterioration. With this technique, we achieved higher drive current pMOSFETs for the same V/sub th/-rolloff and a 13% improvement in drivability for 45 nm pMOSFETs.

ABSTRACT2. 0 keV 11B+, 2.2 keV 49BF2+ ion implanted and 1.0 kV Plasma Doped (PLAD) wafers of a dose of 1E15/cm2 were annealed at various times and temperatures in a variety of ambiente: 600 to 50,000 ppm O2 in N2; 5% NH3 in N2; N2O; N2 or Ar, in order to investigate the effects of the annealing ambient on the formation of ultra-shallow junctions. RGA data was collected during some (if the anneals to assist in identifying the complex surface chemistry responsible for boron out-diffusion. Subsequent to the anneals, ellipsometric, XPS, four-point probe sheet resistance and SJJVIS measurements were performed to further elucidate the effects of the different ambients on the r etained boron dose, the sheet resistance value, the RTP grown oxide layer and the junction depth. In the cases where oxygen was present, e.g. N2O and O2 in N2, an oxidation enhanced diffusion of the boron was observed. This was most dramatic for the N2O anneals, which at 1050°C 10s diffused the boron an additional 283 to 427 Å, depending on the particular doping condition and species. For the case of BF2 implants and PLAD, anneals in 5% NH3 in N2 reduced the junction depth by a nitridation reduced diffusion mechanism. RGA data indicated that the out-diffusion mechanisms for B and BF2 implanted wafers are different, with the BF2 exhibiting dopant loss mechanisms during the 950°C anneals, producing F containing compounds. B implants did not show doping loss mechanisms, ais observed by the RGA, until the 1050°C anneals and these signals did not contain F containing compounds. Equivalent effective energy boron implants of 8.9 keV BF2 vs. 2.0 keV B, however, indicated that the overall effect of the F in the BF2 implants is very beneficial in the creation of ultra-shallow junctions (compared to B implants): reducing the junction depth by 428 Å, and increasing the electrical activation (determined by SRP) by 11.7%, even though the retained dose (resulting from an increased out-diffusion of B), was decreased by 5.4%.

Shallow p+-n junctions in silicon are fabricated by the implantation of 10 keV B+or 50 keV BF 2+ ions at a fluence of 3 × 1015/ cm2through a capping layer of 25-nm SiO 2 . Sheet resistance, contact resistivity, and forward and reverse bias leakage current are measured for various furnace and rapid thermal annealing (RTA) conditions. SIMS profiles are included. RTA allows the simultaneous achievement of junctions with j R_{s}\simeq 50 \Omega/ , and \rho_{c}\simeq 2 \times 10^{-6}\Omega . cm2for junction depths of the order of 0.25 µm as mesured by the traditional bevel-and-strain method.