Optimal Current Ripple PWM for Three-Level Inverter With Common Mode Voltage Reduction

For most medium voltage high power applications, Neutral Point Clamped (NPC) three-level inverter is a preferred choice due to its advantages such as low cost, light weight and compact size. Space vector modulation is widely used in real-time digital control for power converters. It is especially suitable for use in NPC multilevel inverters due to its good harmonic profile, flexibility and easy digital implementation. This thesis focuses on the space vector modulation for high power three-level NPC inverter, where the switching frequency of the semiconductor devices is nominally below 1 OOOHz to reduce the power loss of the switching devices. The conventional space vector modulation (SVM) scheme for the three-level NPC inverter produces even order harmonics in the output voltages, which are not desirable for most industrial applications. In this thesis, the mechanism of even order harmonic generation is analysed. A new space vector modulation scheme, which can eliminate all the even order harmonics, is proposed. The performance of the new design is investigated and simulation results are provided for the verification purpose. The harmonic and THD profiles are compared with those of the conventional SVM scheme. The elimination of even order harmonics is achieved at the expense of a slight increase in the switching frequency. The proposed space vector modulation scheme can be applied to other types of converters for the even order harmonic elimination. An algorithm is developed to mitigate the neutral point potential deviation, which is a common problem in the NPC inverters. The simulation results show that this algorithm is suitable for both conventional and the proposed space vector modulation schemes.

A common-mode (CM) voltage reduction modulation for a three-level full bridge phase-shift DC-DC converter is proposed in this paper. With conventional modulation, the three-level full bridge phase-shift DC-DC converter generates considerable CM voltage. The CM voltage is undesired because it causes CM current noise and deteriorate EMI performance. To solve this problem, methods including bulky EMI filter or additional cancellation circuits are usually used. However, it increases system cost, and reduces efficiency. The proposed modulation method can reduce the CM voltage close to zero and reduce the CM current substantially. The method does not require any additional circuit. The size of EMI filter could also be reduced due to the reduced CM voltage and current. Compared with conventional methods, the proposed CM voltage reduction method has the benefits of effective, low cost and high efficiency. The principle of the proposed modulation method is presented in this paper. The correctness and effectiveness of the method is verified by simulation and experimental results.

Many reduced common mode voltage (CMV) modulation methods have been proposed for three-level inverters. However, most of them suffer from large current distortion because only part of the available base vectors is utilized. The interleaved paralleling can reduce both CMV and the output current distortion, though the CMV reduction is limited and large zero-sequence circulating current (ZSCC) is inevitably caused by the phase-shifted carriers. To further reduce the CMV while maintaining smaller current distortion and ZSCC, a five-level reduced CMV (RCMV) modulation method is proposed in this article, which treats the parallel inverters as a whole. Theoretical analysis reveals that the integrated modulation provides additional base vectors that contribute to smaller total harmonic distortion (THD) of the current, and the selected vectors ensure the nearest-three-vector synthesis and half-reduced CMV. The switching sequences design and neutral point balancing strategy are also developed for dual-parallel three-level inverters, ensuring that the average circulating current is zero and the neutral point voltage is balanced, which are both critical to the proper operation of parallel inverters. Superior performance in terms of CMV, THD, and ZSCC provided by the proposed method in comparison with conventional modulation is verified by comprehensive simulation and experimental results.

Pulse Width Modulated (PWM) inverters produce common mode voltage. The common mode voltage will have adverse effect on the motor bearings. Hence the common mode voltage has to be reduced. This paper presents a modified Sinusoidal Pulse Width Modulation (SPWM) scheme in which two complementary modulating inputs are used to generate the pulses for the switches of a two level, three phase inverter to reduce the common mode voltage. The performance of proposed modulation scheme is evaluated and tested for various switching frequencies. With the proposed modulation scheme the phase voltages appears to be three level voltage which helps in reduction of common mode voltage. A comparative study of common mode voltage with both normal and modified SPWM method is also done and the results are presented in this paper.

The three-level inverter has been widely researched and adopted in industry. This article further proposes a carrier-based modulation method to reduce the common-mode voltage (CMV) and obtain high-quality output currents for three-level inverter with unbalanced neutral-point voltage conditions. In this method, the zero-sequence voltage is calculated by three-phase modulation waves, three-phase output currents, and voltages across the dc-link capacitors. The limitations of the zero-sequence component are carefully considered in order not to generate the basic voltage vector with high CMV magnitudes. In addition, a deadbeat control scheme for controlling the dc-link voltages asymmetrically with the proposed pulsewidth modulation method is presented, and asymmetrical control of dc-link voltages can be realized with fast response. Compared with the conventional space vector modulation (SVM) and the virtual SVM methods, the proposed scheme can reduce the CMV by half. Simulated and experimental results validate the effectiveness of the proposed method.

In wind turbine applications, the common mode voltage induced bearing currents lead to the frequent failures in wind turbines. Thus, it would be beneficial to reduce the common mode voltage in the system to reduce the bearing currents. In this study, a space vector modulation based strategy which aims to achieve low common mode voltage for a wind turbine application using modular multilevel converters is investigated. The impact between the common mode voltage reduction strategy, the circulating currents, the submodule capacitor voltages, and the converter losses are studied as well. It is found that the common mode voltage reduction can be affected by the circulating current control to some extent, however, the target of reducing the common mode voltage can still be achieved. The results show that the peak-to-peak amplitude of the common mode voltage can be decreased by 40% along with the circulating current control in the converter. On the other hand, the total losses inside the converter increase by 82% when using the common mode voltage reduction strategy, and this should be justified from a long-term perspective when considering the life-cycle cost of the system.

The dual T-type multilevel converter (MLC) is an advanced topology with a reduced switching device count compared to a conventional diode clamped converter. This paper proposes a reduced switching state model predictive control (MPC) of a dual T-type drive system considering the DC link capacitor balancing, the common-mode voltage (CMV) along with torque control of an open-ends induction motor. The proposed study addresses the CMV in two different scenarios; i.e., the CMV reduction (CMVR) and CMV elimination (CMVE). A Matlab simulation for the proposed drive system is presented. A dual T-type converter prototype based on Silicon-Carbide discrete MOSFET switch is designed, implemented, and tested in the laboratory. The proposed MPC scheme achieves the torque command as well as balances the dual DC links in an efficient manner. It is observed that the CMVE has some limitation compared to CMVR, particularly at rated speed operation. It is worth mentioning that the proposed reduced switching states technique could reduce the computation time from 5.5 ms to $140~\mu \text{s}$ for CMVR and $70~\mu \text{s}$ for CMVE. In addition, the results demonstrate the effectiveness of CMVR scheme in reducing the harmonic contents, the torque and flux ripples, and converter switching loss compared to the CMVE scheme.

Due to its advantages, the asymmetrical dual three-phase induction motor drive is a strong choice in high-power applications. However, the common-mode voltage produced by the voltage source inverters affects the winding insulation and damages the bearings. Common-mode voltage is also responsible for electromagnetic interference and leakage currents. This paper, therefore, analyses the common-mode voltage produced by the inverter supplying a dual three-phase induction motor drive and proposes a novel modified space vector decomposition-based Space Vector Pulse Width Modulation (SVPWM) technique for common mode reduction. The vector space decomposition-based space vector modulation technique offers excellent flexibility as it reduces the common-mode voltage (CMV) by exploiting the additional degree of freedom in a dual three-phase system. The common-mode voltage (CMV) can be reduced to one-sixth of the DC link voltage compared to the highest CMV, i.e. half of the DC-link voltage produced in conventional space vector modulation. The proposed method is also validated experimentally to demonstrate the effectiveness of the proposed scheme in terms of the amplitude of CMV, pulsations, and total harmonic distortion(THD) in current.

This paper presents a new, simple and generalized approach to calculate flying capacitor currents for an n-level flying capacitor converter without the use of look-up tables. The performance of the proposed method has been studied for a three-, four- and five-level flying capacitor converter in MATLAB/Simulink environment.

Parallel three-level inverters are widely used in high-power applications for increasing the power capacity of the system. However, when multiple three-level T-type inverters are connected to a single dc bus, the zero sequence circulating current (ZSCC) will be generated. For the operation of paralleled inverters, another requirement is to reduce the common mode voltage (CMV) associated with pulsewidth modulation (PWM) method. As these two issues are mutually coupled, the conventional space vector modulation (SVM) and active control methods reported so far cannot address them properly simultaneously. To overcome this limitation, a modified SVM technique is proposed to reduce the CMV, suppress ZSCC, and balance neutral point (NP) voltage. The generating mechanism of the ZSCC with respect to modulation scheme is analyzed. Based on the analysis, the large, medium, small, zero vector modulation method is proposed for reducing ZSCC and balancing the NP voltage with reduced CMV as the same in large, medium, zero vector modulation. Furthermore, the effectiveness of the proposed method is verified by comparing its results with those of the convectional PWM. The results are obtained from simulation and experiments.

The three-level neutral-point-clamped (NPC) quasi-Z-source inverter (qZSI) is a promising power converter for renewable applications, where low total harmonic distortion and adjustable output voltage are highly demanded. Similar to the conventional transformerless three-level NPC inverter, common-mode voltage (CMV) and neutral-point voltage (NPV) issues should be addressed properly for the NPC-qZSI. Thus, this paper proposes a new control strategy for the NPC-qZSI to reduce CMV and balance NPV simultaneously by taking advantage of an additional control freedom enabled by the impedance network, i.e., three types of shoot-through states. The proposed strategy can achieve the CMV reduction by choosing the essential switching vectors with acceptable CMVs, while the NPV can be balanced by rearranging the chosen switching vectors in a switching cycle. Experimental tests are provided, which verify the effectiveness of the proposed strategy in terms of CMV reduction and NPV balancing.

A novel space vector modulation (SVM) strategy for a permanent magnet synchronous machine drive, operating at low switching-to-fundamental frequency ratio, is presented in this paper. The proposed strategy is based on applying more than two active vectors in a switching period, aiming to consider the expected rotation and possible movement from one sector to another of the voltage reference vector within that period. The method is simple as the calculation of the duty cycles is still based on the expressions for a conventional SVM. Current distortion and efficiency calculations are also provided, comparing the proposed SVM with conventional SVM and six-step modulation. The results show that the proposed method generates a current distortion similar to the conventional SVM at high frequency ratios but much lower at low frequency ratios. Moreover, comparing with six-step modulation, the current distortion generated by the proposed SVM is always lower, independent of the frequency ratio. On the other hand, the efficiency of the inverter obtained with the proposed SVM is higher than the one obtained with conventional SVM. The effectiveness of the proposed strategy is validated via simulations and experiments.

Due to the ever increasing use of Variable Frequency Drives (VFDs) which involves fast switching converters, focus on reducing the Common Mode Voltage (CMV) is picking up pace. Moreover, the application of SiC power electronics switches, which can switch at much higher switching frequencies than conventionel IGBTs, has refocused the attention on converter redesign to mitigate EMI/EMC issues. The reduction in CMV is necessary to limit the Common Mode Currents (CMC) which in turn reduces the inverter induced bearing currents and shaft voltage. This paper introduces a new scheme, which modulates the shift in the carrier wave for eliminating the highest peaks in CMV. Design, analysis, and simulations have been performed and will be discussed here in details. This new method is compared with the conventional PWM methods and to other similar methods for reducing CMV.

In this paper, a new space vector modulation (SVM) strategy is presented to reduce the output common-mode voltage (CMV) for direct matrix converters. This method modifies the traditional singular value decomposition modulation to enable the usage of switch vectors with 120° phase shift, then substitutes two of the corresponding switch states by an orientation switch state which connects every input to one output phase. Since those orientation switch states have zero CMV at the output side of matrix converters, by this mean, not only the peak value but also the voltage transitions of the CMV are decreased dramatically. Besides, the improvement of the modulation can be implemented by some minor modification in software, and thus not additional costs in hardware are needed. Simulation results are shown to corroborate the effectiveness of the proposed method.

—The space vector modulation technique is an optimal pulse-width modulation technique used for inverter control. This article presents a neuro-fuzzy-based space vector modulation technique for a three-level inverter fed induction motor. It uses a hybrid learning algorithm (combination of back-propagation and least-squares methods) for training the input–output data pattern. The training data for neuro-fuzzy-based space vector modulation are generated from the conventional simplified space vector modulation method. The proposed scheme uses the space vector rotation angle and change of rotation angle information as input and generated duty ratios as output. The dynamic and steady-state performance of a neuro-fuzzy-controlled induction motor drive is compared with the conventional space vector modulation and neural network-based space vector modulation methods. The simulation results obtained are verified experimentally using a dSPACE kit (DS1104). The performance measure in terms of the total harmonic distortion of inverter line–line voltage of the neuro-fuzzy-based system is compared with the neural network-based space vector modulation and conventional space vector modulation methods.