Optimal Extension Field Inversion in the Frequency Domain

We implemented elliptic curve cryptography in the frequency domain on the MSP430 constrained microcontroller. Our implementation of 169-bit elliptic curve cryptography (ECC) on MSP430, one of the most popular microcontrollers for wireless sensor network (WSN) nodes, performs an ECC scalar point multiplication operation, for random points, in only 1.55 ms which is similar to or faster than existing implementations. To our knowledge, this work proposes the first ever software implementation of ECC in the frequency domain on a constrained low-power microcontroller.

The security of Internet of Things (IoT) devices is one of the most important problems to be addressed by the cryptographers and security engineers. The processing ability of IoT devices is limited, therefore light-weight and secure cryptographic tools are necessary for security of them. This paper shows the implementation of 256-bit Elliptic Curve Cryptography (ECC) on an 8-bit microcontroller. The proposed implementation applies towering technique for extension field of degree 32 with a certain 8-bit prime characteristic instead of the 256-bit prime characteristic. It enables to execute 256-bit ECC operations without complicated multiple-precision arithmetic on small computers like 8-bit microcontrollers. This approach efficiently realizes the scalability of the ECC encryption strength. In addition, the authors use a twisted Montgomery curve with a Montgomery ladder technique which enables fast calculations without inversions referring to Curve25519. It is considered resistant to the Side Channel Attack (SCA) since it applies the Montgomery ladder technique for scalar multiplication (SCM). This ECC implementation on Arduino UNO, an 8-bit microcontroller board, can be utilized for a key agreement protocol among IoT devices.

Elliptic curve cryptography is a rather new, efficient technology for security. However, its implementation is complex and software versions can be prohibitively slow. The main original contribution of this paper is the proposition of a highly parameterizable soft intellectual property core that implements all the operations needed to perform elliptic curve cryptography in hardware. This core supports several standardized elliptic curves. Here, finite field operations use only affine coordinates, which keeps interoperability with software implementations. Also, core operators such as the finite field multiplier and inversion are highly configurable, to enable fulfilling constraints of area or performance, according to what is relevant to each application. The core can thus serve several different purposes, through the setting of parameters that pick the adequate elliptic curve and others that control the finite field multiplier and inversion operator characteristics. Results obtained by synthesizing the core with different parameters for Xilinx FPGAs and 65nm CMOS ASICs show that the exploitable design space is ample: implementations can take from 17 to 5,800μs to execute a point multiplication, taking from 5.7 to 162.2 thousand LUTs in FPGAs or from 16,6 to 360,7 thousand gates in ASICs.

Blommer, Otto, and Seifert presented a fault attack on elliptic curve scalar multiplication called the Sign Change Attack, which causes a fault that changes the sign of the accumulation point. As the use of a sign bit for an extended integer is highly unlikely, this appears to be a highly selective manipulation of the key stream. Here we describe two plausible fault attacks on a smart card implementation of elliptic curve cryptography.

Elliptic curve cryptography (ECC) is an excellent candidate for secure embedded multimedia applications due to its small key size and high security protection. The performance profiling of the ECC implementation, such as execution time and data cache stalls, on TriMedia TM1300 and Intel Pentium 4 is conducted in this research. Based on this study, we identify the main bottlenecks of the EEC implementation, and propose some favorable micro-architecture for this application. Moreover, several integer multiplication schemes are presented for the TM1300 processor for performance enhancement. In particular, the FIR-based multiplication is built with the special FIR instruction provided by TM1300. The performance improvement of the proposed schemes is reported and discussed. Overall, we aim at providing a good understanding of the system architecture of secure embedded multimedia applications, hardware and software cryptography implementation with ECC as an example.

Wireless sensor networks (WSNs) are largely deployed in different sectors and applications, and Elliptic Curve Cryptography (ECC) is proven to be the most feasible PKC for WSN security. ECC is believed to provide same level of security such as RSA with a much shorter key length, and thus they seem to be ideal for applications with small resources such a sensor network, smartcard, RFID, etc. However, like any other cryptographic primitive, ECC implementations are vulnerable to Power Analysis Attacks (PAAs) that may reveal the secret keys by exploiting leaked power consumption from running cryptographic devices (e.g. smart cards, mobile phones etc.). In this paper, we present a comprehensive study of major PAAs and its countermeasures on ECC cryptosystems. In addition, this paper describes critical concerns to be considered in designing PAAs on ECC particular for WSNs, and illustrates the need to conduct, in the near future, intensive researches for the development of these specific PAAs.

Wireless sensor networks (WSNs) pose a number of unique security challenges that demand innovation in several areas including the design of cryptographic primitives and protocols. Despite recent progress, the efficient implementation of Elliptic Curve Cryptography (ECC) for WSNs is still a very active research topic, and techniques to further reduce the time and energy cost of ECC are eagerly sought. This paper presents an optimized ECC implementation that we developed from scratch to comply with the severe resource constraints of 8‐bit sensor nodes such as the MICAz and IRIS motes. Our ECC software uses Optimal Prime Fields as underlying algebraic structure and supports two different families of elliptic curves, namely, Weierstraß‐form and twisted Edwards‐form curves. Due to the combination of efficient field arithmetic and fast group operations, we achieve an execution time of 5.3·106 clock cycles for a full 160‐bit scalar multiplication on an 8‐bit ATmega128 microcontroller, which is more than three times faster than the widely used TinyECC library. Our implementation also shows that the energy cost of scalar multiplication on a MICAz (or IRIS) mote amounts to just 17.34mJ when using a twisted Edwards curve over a 160‐bit Optimal Prime Field. This result further demonstrates the advantage of special family of elliptic curves for resource‐constrained environments. Copyright © 2015 John Wiley & Sons, Ltd.

Wireless Sensor Networks (WSNs) pose a number of unique security challenges that demand innovation in several areas including the design of cryptographic primitives and protocols. Despite recent progress, the efficient implementation of Elliptic Curve Cryptography (ECC) for WSNs is still a very active research topic and techniques to further reduce the time and energy cost of ECC are eagerly sought. This paper presents an optimized ECC implementation that we developed from scratch to comply with the severe resource constraints of 8-bit sensor nodes such as the MICAz and IRIS motes. Our ECC software uses Optimal Prime Fields (OPFs) as underlying algebraic structure and supports two different families of elliptic curves, namely Weierstraß-form and twisted Edwards-form curves. Due to the combination of efficient field arithmetic and fast group operations, we achieve an execution time of 5.8 · 106 clock cycles for a full 158-bit scalar multiplication on an 8-bit ATmega128 micro-controller, which is 2.78 times faster than the widely-used TinyECC library. Our implementation also shows that the energy cost of scalar multiplication on a MICAz (or IRIS) mote amounts to just 19~mJ when using a twisted Edwards curve over a 160-bit OPF. This result compares fairly well with the energy figures of two recently-presented hardware designs of ECC based on twisted Edwards curves.

With the rapid development of cloud computing, e-commerce, authentication among multi-robot systems, the highspeed implementation of Elliptic Curve Cryptography (ECC) is in widespread use. The performance of ECC is decided by the design of scalar point multiplier, which is one of the most time-consuming component. This paper presents a full set of methods to achieve an ultra high-speed scalar point multiplier, its Scalar Point Multiplication (SPM) is optimized comprehensively in terms of speed-first design approach by concurrently implementing the Point-add (PA) and Point-double (PD) algorithms, improving large integer modular inversion algorithm and large integer modular multiplication algorithm. Finally, Montgomery domain operation and Non-Adjacent Form (NAF) encoding theory are applied to enhance the speed of scalar point multiplier. In the VLSI design, a high-speed $\pmb{256\times 256}$ -bit scalar point multiplier is achieved based on SMIC's 65nm process. It can complete single calculation of SPM within 12.5us on average, in other word, 80,000 times of SPM can be computed in one second. Compared to the scalar point multiplier realized by other publications based on VLSI, the reports for circuits synthesis show that our multiplier is optimal in terms of $AT^{2}$ and ultrafast in terms of speed.

Designing efficient and secure implementations of Elliptic Curve Cryptography (ECC) has attracted enormous interest from both theoreticians and practitioners. The main contenders in terms of performance are curves defined over binary extension fields or large prime characteristic fields. In addition to the efficiency requirements, security advantages such as implementation simplicity and resistance to side-channel attacks are receiving increasing attention in research and commercial applications. In this paper, we keep pushing in this direction and study efficient implementation of regular scalar multiplication algorithms for binary curves equipped with efficient endomorphisms. Our focus is on implementing the Galbraith-Lin-Scott (GLS) family of binary curves by exploring the space of different models and laddering algorithms, for their high performance, reasonable implementation simplicity, lower memory consumption and side-channel resistance. Our results demonstrate that laddering implementations can be competitive with window-based methods by obtaining a new speed record for laddering implementations of elliptic curves on high-end Intel processors.

We propose to represent a scalar in the form of d (1/2)(superscript a)3(superscript b), where a and b are integers and d is an odd integer belonging to a given set. This representation is a combination of the extended double-base number system (DBNS) and the double-base chain representation using powers of 1/2 and 3. Experimental results show that our approach leads to a shorter DBNS expansion and a lower complexity in elliptic curve scalar multiplication, with the cost of only a few pre-computations and storages. This contributes to the efficient implementation of elliptic curve cryptography (ECC).

High-speed hardware implementations of Elliptic Curve Cryptography: A survey

On the low-end embedded processors, the implementations of Elliptic Curve Cryptography (ECC) are considered to be a challenging task due to the limited computation power and storage of the low-end embedded processors. Particularly, the multi-precision multiplication and squaring operations are the most expensive operations for ECC implementations. In order to enhance the performance, many works presented efficient multiplication and squaring routines on the target devices. Recent works show that 128-bit security level ECC is available within a second and this is practically fast enough for IoT services. However, previous approaches missed the other important storage issues (i.e., program size, ROM). Considering that the embedded processors only have a few KB ROM, we need to pay attention to the compact ROM size with reasonable performance. In this article, we present very compact and generic implementations of multiplication and squaring operations on the 16-bit MSP430X processors for the ECC. The implementations utilize the new 32-bit multiplier and advanced multiplication and squaring routines. Since the proposed routines are generic, the arbitrary length of operand is available with high-speed and small code size. With proposed multiplication and squaring routines, we implemented Curve25519 on the MSP430X processors. The scalar multiplication is performed within 6,666,895 clock cycles and 4,054 bytes. Compared with previous works based on the speed-optimized version, our memory-efficient version reduces the code size by 59.8%, sacrificing the execution timing by 20.5%.

E03: A new systolic architecture for multiplication in GF(2n)

This research addresses the computationallyeffective implementation of cryptographic protocols based on elliptic curves, and targets in particular cryptosystems that should be hosted on embedded programmable processors. In principle, the implementation of Elliptic Curve Cryptography
\n(ECC) requires one to deal with different design options, which stem from the available degrees of freedom: elliptic curve family, coordinate system, and point multiplication procedure. On the other hand, theoretical studies already proved that exist only a few setups leading to computational efficient implementations. The goal of present paper is to analyze from an applicative point of view such setups, which mainly involve two specific
\nfamilies of elliptic curves: Edwards curves and extend Jacobi quartic curves. The presented experimental session shows a few interesting outcomes; first, ECC schemes implemented by using either Edwards curves or extended Jacobi quartic curves can obtain remarkable performances in terms of computational efficiency also on low-cost, low-resources processors. Second, the experiments showed that in some cases the number of Fp operations is not enough to accurately estimate the overall performance of an ECC-based cryptosystem.