Optimal loop bandwidth design for low noise PLL applications

In microwave systems, the phase noise is well known to be a significant source of degradation especially for low data rate transmission, giving rise to a significant irreducible error rate. In an earlier study [1,2] based on the European Space Agency's Olympus Satellite 30/20 GHz payload parameters, it was found that several thousands of simultaneous transmissions of 50 to 200 bits/sec each could be supported from hand-held pico-terminal earth stations. It is important to use the most appropriate modulation scheme in the presence of oscillator phase noise for such low data rate systems. It is generally assumed that noncoherent or differentially coherent modulation schemes will perform best in applications where the coherence time of the oscillators is short compared to the bit period. However, our analysis of these schemes has shown that they are subject to irreducible error rates and minimum useable data rates. This has led us to reconsider coherent BPSK (CPSK). It is shown that the choice of the optimum noise bandwidth of the phase locked loop (PLL) in the carrier recovery circuit is very important when considering the coherent schemes. The PLL bandwidth must be wide enough to track the oscillator phase noise at its input, but, on the other hand, it must be as narrow as possible to exclude the thermal noise. Results show that coherent BPSK in the phase noise contaminated channel is also subject to an irreducible error rate, which increases as the noise bandwidth is reduced. For the optimum loop bandwidth, however, this appears to be lower than the corresponding figure for DPSK [3]. There is a minimum useable data rate for any given bit error rate (BER) requirement. Results of a complete analysis are presented in the form of BER versusE b/N o plots.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

Ionospheric scintillation occurs for transionospheric radio waves propagating through random ionospheric irregularities, which affect the phase and/or amplitude observations made by the receiver. Generally, the scintillation induces excess carrier phase jitter in the phase lock loop (PLL) of the GPS receiver, and strong scintillation can cause a conventional PLL (ATAN [arctangent method], constant bandwidth Bn = 10 Hz) to lose phase lock resulting in no GNSS signal available at that time from the satellite path(s) affected. A PLL with a larger bandwidth is one solution to mitigate this but at the expense of extra phase noise, and this may not be an optimal solution during weak scintillation conditions. This study uses a novel WBMod (Wide Band Modeling) assisted PLL for robustness of availability of GPS services with lower introduction of extra phase noise. At the initial stage, an optimal PLL bandwidth is predicted using WBMod to stabilize the PLL during strong phase scintillation. A FAB (Fast Adaptive Bandwidth) PLL is used to minimize the phase error. To investigate this approach, a realistic scintillated signal is produced using 50 Hz raw GPS signal observations (carrier phase and intensity) collected at Yellowknife (Yell, 64.48° N, -114.52° E) in a Matlab-based GPS software receiver.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-/spl mu/m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively.

Phase locked loop (PLL) and Park transformation largely affects the stability of a grid-inverter system. Impedance-based approach is employed to analyze the effect of PLL to stability in this paper. Self-admittance and accompanying admittances are set up to represent the inverter including the PLL effect, and Nyquist criterion is employed to analyze the system stability. An asymmetric current control scheme is proposed to alleviate the PLL effect on stability of the grid-inverter system. The proposed control scheme is simple and practical in the sense that it is derived using the existing current controller. An inverter admittance model including the PLL effect and asymmetric current controller is constructed to evaluate the stability of the inverter-grid system. The relationship between the asymmetric ratio and PLL bandwidth is established to ensure the stability. Experimental results demonstrate that the proposed asymmetric control scheme achieves the stability without sacrificing the PLL bandwidth.

Optimization analysis on the bandwidth algorithm for the phase-locked loop (PLL) in OTU

As large-scale renewable energy sources are increasingly integrated into AC grids via voltage source converters (VSCs), the transient synchronization stability of phase-locked loop (PLL)-based VSCs during fault ride-through is gaining more attention. Most existing studies assume that the positive and negative sequence separation and current control dynamics are much faster than the PLL dynamics, thereby neglecting their impact on the transient synchronization stability of the system. However, when the PLL bandwidth is relatively large, ignoring the positive and negative sequence separation and current control dynamics may result in incorrect stability assessments. To address this issue, this paper first considers the multiple control loop coupling, including positive and negative sequence separation, current control, and PLL, to construct a full-order nonlinear mathematical model of the VSC grid-connected system under asymmetric fault conditions. Based on this, the phase trajectory method is employed to analyze the transient synchronization stability of the system. Additionally, this full-order mathematical model is used to determine the PLL bandwidth boundary beyond which the effects of positive and negative sequence separation and current control dynamics cannot be neglected. Finally, PSCAD/EMTDC simulation results validate the effectiveness of the theoretical analysis presented in this paper.

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

Electric vehicles (EVs) are a promising solution to reduce carbon dioxide (CO2) emissions, but this reduction depends on the fraction of renewable sources used to generate electricity. Wind energy is thus a vital candidate and has experienced a remarkable surge recently, establishing itself as a leading renewable power source worldwide. The research on Direct-Driven Permanent Magnet Synchronous Generator (PMSG)-based type 4 wind farms has indicated that the Phase-locked Loop (PLL) bandwidth significantly impacts Sub-Synchronous Resonance (SSR). However, the influence of PLL architecture on SSR remains unexplored and warrants investigation. Therefore, this paper investigates PLL architectural variations in PLL Loop Filter (LF) to understand their impact on SSR in type 4 wind farms. Specifically, an in-depth analysis of the Notch Filter (NF)-based enhanced PLL is conducted using eigenvalue analysis of the admittance model of a PMSG-based type 4 wind farm. The findings demonstrate that the NF-based enhanced PLL exhibits superior performance and improved passivity in the sub-synchronous frequency range, limiting the risk of SSR below 20 Hz. Additionally, Nyquist plots are employed to assess the impact on system stability resulting in increased stability margins. In the future, it is recommended to further investigate and optimize the PLL to mitigate SSR in wind farms.

A d-axis current error compensation method based on coupling mechanism for Grid-Connected inverters under weak grid

Phase-locked loops (PLLs) are nonlinear automatic control circuits widely used in telecommunications, computer architecture, gyroscopes, and other applications. One of the key problems of nonlinear analysis of PLL systems has been stated by Floyd M. Gardner as being “to define exactly any unique lock-in frequency.” The lock-in range concept describes the ability of PLLs to reacquire a locked state without cycle slipping and its calculation requires nonlinear analysis. The present work analyzes a second-order type 2 phase-locked loop with a sinusoidal phase detector characteristic. Using the qualitative theory of dynamical systems and classical methods of control theory, we provide stability analysis and suggest analytical lower and upper estimates of the lock-in range based on the exact lock-in range formula for a second-order type 2 PLL with a triangular phase detector characteristic, obtained earlier. Applying phase plane analysis, an asymptotic formula for the lock-in range which refines the existing formula is obtained. The analytical formulas are compared with computer simulation and engineering estimates of the lock-in range. The comparison shows that engineering estimates can lead to cycle slipping in the corresponding PLL model and cannot provide a reliable solution for the Gardner problem, whereas the lower estimate presented in this article guarantees frequency reacquisition without cycle slipping for all parameters, which provides a solution to the Gardner problem.

This paper describes a low jitter phase-locked-loop (PLL) with a 4/sup th/ order control path, and a dual control voltage ring oscillator. Near constant voltage controlled oscillator (VCO) gain over process variations, in addition to compensation for feedback ratio variation, allows improved control of the PLL bandwidth. The PLL exhibits improved noise immunity with a wide (5:1) VCO frequency range, without the need for band switching or calibration routines. This PLL is fabricated in a 0.18 /spl mu/m CMOS logic process and exhibits <4 ps rms accumulated jitter.

The phase locked loop (PLL) is a control system that compares the phase of the output signal with that of the input signal and proportionally varies its output based on the phase difference between them. PLL most prolifically finds its applications in frequency generation, clock and data recovery, carrier frequency generation in modulation and demodulation, frequency synthesizers, jitter and skew reduction, and many more. Mixed-signal and digital circuits employ PLL for clock generation to get the synchronous transactions with the clock. So it is mandatory to properly design the PLL to obtain minimum jitter on the clock edges. The PLL designed in this work was based on the famous charge-pump (CP) architecture and was implemented using the semiconductor laboratory (SCL) 180 nm technology in Cadence Virtuoso. This work uses NOR-based PFD using TSPC latches, Transmission gate CP, Current Starved VCO, and TSPC-based divider circuit. The proposed model of PLL has phase noise of the PLL as −113 dBc/Hz, the power consumption of the total PLL as 3.2 mW at 1.8 V power supply with deterministic jitter of about 5.62 ps and the settling time of the control voltage as 850 ns.

We study the dynamics and characterize the bifurcation structure of a phase-locked loop (PLL) device modeled by a third-order autonomous differential equation with sinusoidal phase detector. The development of this work was performed using rigorous analysis and numerical experiments. Through theoretical analysis the bifurcation structures related to two fundamental equilibrium points of the system are described. By using extensive numerical experiments we investigate the intricate organization between periodic and chaotic domains in parameter space (named here parameter plane as the PLL model has only two control parameters) and obtain two following remarkable findings: (i) there are self-organized generic stable periodic structures along specific directions in parameter plane, whose periods are defined by a mathematical rule and, (ii) the existence of transient chaos phenomenon responsible for long chaotic temporal evolution preceding the asymptotic (periodic) dynamics for some particular control parameter pairs is characterized. Our theoretical and numerical results present an astonishing concordance. We believe that the present study, specially the parameter plane analysis, may have a great importance to experimental studies and general applications involving PLL devices when, for example, one would like to avoid the chaotic regimes.

Peripheral sensory activity follows the temporal structure of input signals. Central sensory processing uses also rate coding, and motor outputs appear to be primarily encoded by rate. I propose here a simple, efficient structure, converting temporal coding to rate coding by neuronal phase-locked loops (PLL). The simplest form of a PLL includes a phase detector (that is, a neuronal-plausible version of an ideal coincidence detector) and a controllable local oscillator that are connected in a negative feedback loop. The phase detector compares the firing times of the local oscillator and the input and provides an output whose firing rate is monotonically related to the time difference. The output rate is fed back to the local oscillator and forces it to phase-lock to the input. Every temporal interval at the input is associated with a specific pair of output rate and time difference values; the higher the output rate, the further the local oscillator is driven from its intrinsic frequency. Sequences of input intervals, which by definition encode input information, are thus represented by sequences of firing rates at the PLL's output. The most plausible implementation of PLL circuits is by thalamocortical loops in which populations of thalamic "relay" neurons function as phase detectors that compare the timings of cortical oscillators and sensory signals. The output in this case is encoded by the thalamic population rate. This article presents and analyzes the algorithmic and the implementation levels of the proposed PLL model and describes the implementation of the PLL model to the primate tactile system.