Optimal Path Length for Octagon-Cell Interconnection Networks: Fundamental Theorems with Proofs

For the requirements of indoor mobile robot planning global optimal path, traversing multi goals and dynamic obstacle avoidance, a multi-goal global dynamic path planning method is proposed in this paper, which is combined improved A * algorithm, traveling salesman problem (TSP), and dynamic window approach (DWA). The improved A* is used to plan the optimal collision-free path between two goals, and a key node selection scheme is used to remove the redundant nodes. And the TSP distance search square matrix is formed by using the optimal path length between the two goals, and the optimal order of traversing all goals is determined by ant colony algorithm. Then DWA evaluation function is constructed, which is considered with the global optimal path and speed, and real-time obstacle avoidance. On the basis of ensuring the global optimality of the planned path, all goals are traversed at the optimal speed, and the path is smoother, the ability of dynamic obstacle avoidance is improved. The simulation results demonstrate that compared with traditional methods, the proposed method is more efficient, smoother path, real-time dynamic obstacle avoidance, which has applications in autonomous navigation of multi targets mobile robots.

A photonic packet switching device is designed for WDM based optical slotted ring networks which are suitable for B-ISDN access network and LAN/MAN. For the design, we devised a fiber optic delay line matched filter as a means of address filtering at the destination node and developed an efficient address decoding algorithm to accommodate the maximum available number of nodes in the ring network. Based on the algorithm, the maximum available number of node addresses in the ring is 3,432 for the case of 16-bit address. The design objectives of the photonic packet switching device are to eliminate the optical-to-electrical conversion at the address processing, to remove optical data from the ring at the destination nodes so that the slots can be reused a number of times in a rotation, and to be compatible with B-ISDN based on ATM concerning services, bit rate, interface, and switching node. The network architecture using the photonic packet switching device is also described. The simulation results show that the major part of the cell transfer delay in the network is coming from the propagation delay from a source to a destination. It was also observed that the average transfer delay characteristic of the network depends upon the aggregated transmission capacity of the network.

For the issues of the ant colony algorithm (ACO) to solving the problems in mobile robot path planning, such as the slow optimization speed and the redundant paths in planning results, a high-precision improved ant colony algorithm (IPACO) with fast optimization and compound prediction mechanism is proposed. Firstly, aiming at maximizing the possibility of optimal node selection in the process of path planning, a composite optimal node prediction model is introduced to improve the state transition function. Secondly, a pheromone model with initialize the distribution and “reward or punishment” update mechanism is used to updates the global pheromone concentration directionally, which increases the pheromone concentration of excellent path nodes and the heuristic effect; Finally, a prediction-backward mechanism to deal with the “deadlock” problem in the ant colony search process is adopted in the IPACO algorithm, which enhance the success rate in the ACO algorithm path planning. Five groups of different environments are selected to compare and verify the performance of IPACO algorithm, ACO algorithm and three typical path planning algorithms. The experimental simulation results show that, compared with the ACO algorithm, the convergence speed and the planning path accuracy of the IPACO algorithm are improved by 57.69% and 12.86% respectively, and the convergence speed and the planning path accuracy are significantly improved; the optimal path length, optimization speed and stability of the IPACO algorithm are improved. Which verifies that the IPACO algorithm can effectively improve the environmental compatibility and stability of the ant colony algorithm path planning, and the effect is significantly improved.

Reviews and experimental verification have found that existing solution methods can be used to solve UAV path planning problems, but each approximate solution has its own advantages and disadvantages. For example, ant colony algorithm easily falls into the local optimum in the process of realizing path planning. In order to prevent too low pheromones on the longer path and too high pheromones in the shorter path, the upper and lower limits of pheromones as well as their volatile factors are set to avoid falling into the local optimum. Secondly, multi-heuristic factors are introduced, and the overall length of the path serves as an adaptive heuristic function factor that determines the probability of state transition, which affects the probability of ants choosing the corresponding path. The experimental results show that the path length planned by the improved algorithm is 93.6% of the original algorithm, and the optimal path length variance is only 14.22% of the original algorithm. The improved ant colony algorithm shortens the optimal path length and solves the UAV path planning problem in terms of local optima. At the same time, multiple enlightening factors are introduced to increase the suitability of UAV for complex environments and improve the performance of UAV.

A novel parameterization concept for structural truss topology optimization is presented in this article that enables the use of evolutionary algorithms in design of large-scale structures. The representational power of Boolean networks is used here to parameterize truss topology. A genetic algorithm then operates on parameters that govern the generation of truss topologies using this random network instead of operating directly on design variables. A genetic algorithm implementation is also presented that is congruent with the local rule application of the random network. The primary advantage of using a Boolean random network representation is that a relatively large number of ground structure nodes can be used, enabling successful exploration of a large-scale design space. In the classical binary representation of ground structures, the number of optimization variables increases quadratically with the number of nodes, restricting the maximum number of nodes that can be considered using a ground structure approach. The Boolean random network representation proposed here allows for the exploration of the entire topology space in a systematic way using only a linear number of variables. The number of nodes in the design domain, therefore, can be increased significantly. Truss member geometry and size optimization is performed here in a nested manner where an inner loop size optimization problem is solved for every candidate topology using sequential linear programming with move-limits. The Boolean random network and nested inner-loop optimization allows for the concurrent optimization of truss topology, geometry, and size. The effectiveness of this method is demonstrated using a planar truss design optimization benchmark problem.

Highly parallel systems are receiving significant attention to solve the large and complex problems. This has resulted in the emergence of many attractive interconnection network topologies. This paper introduces a new processor interconnection topology called STH (Scalable Twisted Hypercube) to counter the poor scalability of twisted hypercube. Its suitability for use as multiprocessor interconnection networks has also been explored. The various properties of the proposed topology have been analyzed and it has been compared with some other highly scalable topologies of interest on a number of interconnection networks evaluation parameters. With reduced diameter, better average distance, low traffic density, low cost, maximum number of links, high bisection width and tremendous scalability, STH is more suitable for Massively Parallel Systems. Procedures for routing and broadcasting on the proposed topology have also been discussed and a simple routing algorithm has been presented. The proposed interconnection network provides a great architectural support for parallel computing due to the concurrent existence of multiple LST(m) and TQn.

Interconnection networks have been deployed as the communication fabric in a wide spectrum of parallel computer systems, ranging from chip multiprocessors (CMPs) and embedded multicore systems-on-a-chip (SoCs) to clusters and server blades. Recent technology trends have permitted a rapid growth of chip resources, faster clock rates, and wider communication bandwidths, however, these trends have also led to an increase in power consumption that is becoming a key limiting factor in the design of such scalable interconnected systems. Power-aware networks, therefore, need to become inherent components of single and multi-chip parallel systems. In the hardware arena, recent interconnection network power-management research work has employed limited-scope techniques that mostly focus on reducing the power consumed by the network communication links. As these limited-scope techniques are not tailored to the applications running on the network, power savings and the corresponding impact on network latency vary significantly from one application to the next as we demonstrate in this paper; in many cases, network performance can severely suffer. In the software arena, extensive research on compile-time optimizations has produced parallelizing compilers that can efficiently map an application onto hardware for high performance. However, research into power-aware parallelizing compilers is in its infancy. In this paper, we take the first steps toward tailoring applications' communication needs at run-time for low power. We propose software techniques that extend the flow of a parallelizing compiler in order to direct run-time network power reduction. We target network links, a significant power consumer in these systems, allowing dynamic voltage scaling (DVS) instructions extracted during static compilation to orchestrate link voltage and frequency transitions for power savings during application run-time. Concurrently, an online hardware mechanism measures network congestion levels and adapts these off-line DVS settings to maximize network performance. Our simulations over three existing parallel systems, ranging from very fine-grained single-chip to coarse-grained multi-chip architectures, show that link power consumption can be reduced by up to 76.3%, with a minor increase in latency, ranging from 0.18 to 6.78% across a number of benchmark suites.

Path planning is a fundamental component in the development of robotics, autonomous navigation, and intelligent systems, playing a pivotal role in the functioning of smart cities. Within the realm of smart cities, where infrastructure is becoming increasingly interconnected, efficient path planning algorithms are essential for optimizing traffic flow, reducing congestion, and ensuring the seamless movement of people and goods. Among various path planning algorithms, the A* algorithm remains one of the most widely used approaches due to its completeness and optimality under consistent heuristics. However, traditional A* suffers from several limitations when applied to complex 3D environments, including uniform neighbor expansion, fixed-resolution grids, and overly simplistic heuristic functions. These drawbacks often lead to excessive computation, suboptimal paths, and failure in cluttered or large-scale scenarios. To address these challenges, we propose a direction aware and self-adaptive A* algorithm named DASA*, an enhanced A* based path planning framework. Firstly, we propose an adaptive hierarchical direction-aware neighborhood selection mechanism. Driven by a lightweight stagnation detector based on open-set growth rate, this mechanism enables seamless automatic switching of neighborhood expansion from narrow conical angles to full 26-neighbourhood coverage. This fundamentally resolves the search incompleteness inherent in traditional fixed-conical-angle directional A* algorithms at the mechanism level, significantly enhancing planning success rates and efficiency. Secondly, a resolution-adaptive search strategy dynamically adjusts planning granularity based on local obstacle density. It advances rapidly with coarse granularity in sparse areas while switching to fine granularity for precise obstacle avoidance in dense zones, achieving an optimal balance between efficiency and safety in heterogeneous environments. Moreover, the designed learnable heuristic plugin interface enables seamless integration of PPO models trained on spatio-semantic features. This provides more informative, purposeful, and forward-looking heuristic guidance, further accelerating convergence towards optimal paths. Finally, we have devised a delayed path adjustment strategy that simplifies trajectories by omitting redundant waypoints through a deferred update mechanism. Subsequently, cubic B-spline interpolation is applied to smooth the path, ensuring curvature continuity and effectively preventing abrupt turns and unnatural maneuvers. This enhances both the fluidity and kinematic plausibility of the trajectory. Subsequently, Extensive experiments in simulated 3D environments demonstrate that DASA* outperforms conventional A* and Other mainstream algorithms in terms of planning time, length of optimal path, and success rate. The proposed framework provides a practical and extensible foundation for real-world applications such as UAV navigation, mobile robotics, and autonomous inspection in complex terrains.

An interconnected silver network composed of grain boundary layers with each layer about 100 nm thick was spontaneously formed inside a silica matrix when a sol–gel sample containing silver ion and polyethylene glycol was dried and heat‐treated. The minimum spacing of the silver structure was ≈15 µm and the density of the silver structure was related to the drying rate, which can be controlled by either drying temperature or vacuum drying time. It was found that the shrinkage‐induced stress during the drying process results in microcracks where the crack surfaces serve as a 3D template for silver to develop into interconnected network when the sample is annealed at 160 °C. The ability to control the density of microcracks and to utilize the microcracks as silver template suggests that this method can be utilized to (1) create interconnected silver network of desired density in silica materials, (2) visualize the microcracks of sol–gel materials, and (3) reinforce and repair the defects after microcracks have formed.

The increasing of the signaling technology motivated the research community to find alternative solutions to replace the sequential computing systems. These systems reached their limits, and it became an infeasible choice to manage the computational grand challenges. Thereby, many types of research have been conducted to improve a system with special characteristics able to cope with the new technology. Massively parallel computer (MPC) systems have been emerged to solve the complex computing challenges in parallel and concurrently. The performance of these systems is affected by the structure of the underlying interconnection network. Therefore, many designs of interconnection networks topologies have been presented looking for an optimal one. In this paper, we present the architecture of MMN which is a hierarchical interconnection network. The static and dynamic performance parameters of MMN have been evaluated in previous studies, and it provided good results compared to the conventional interconnection network topologies. This paper will focus on evaluating and determining the static cost-effective parameter of MMN which is the product of the relation between the node degree, network diameter, wiring complexity, and the total number of nodes in each network.

Making use of a newly available rapid-tuning diode laser operating at wavelengths up to 2.9 µm, an absorption-based temperature sensor was developed for in situ measurements in low-pressure flames. Based on the systematic analysis of H2O vapor transitions in the fundamental vibrational bands (ν1 and ν3) of H2O in the range of 2.5–3.0 µm, an optimal closely-spaced spectral line pair near 2.9 µm was selected for its temperature sensitivity in the range of 1000–2500 K. The narrow-linewidth room-temperature laser was scanned repetitively across these spectral features at 5 kHz, enabling fast, accurate temperature sensing. Use of the temperature sensor was investigated in low-pressure flames supported on a McKenna burner at 15, 25 and 60 Torr. To avoid absorption by the cold gases in the flame edges and the recirculation region between the burner and the vacuum chamber wall, a variable-path in situ probe was designed and an optimal path length was determined to accurately measure the flame centerline temperature. Different flame conditions were investigated to illustrate the potential of this sensor system for sensitive measurements of combustion temperature in low-pressure flames.

The principal advantage of incremental A* algorithms for precomputing and maintaining routes for mobile robotic vehicles is the completeness and optimality of the approach. However, the computational burden becomes unreasonable when large worlds are modeled or fine resolution is required, since the complexity is bound by the area modeled. This problem is compounded when multiple vehicles and multiple goals are involved, since routes to each goal from each vehicle must be maintained. This paper presents a massively parallel incremental A* algorithm suitable for implementing in VLSI. The number of iterations of the parallel algorithm is bound by the optimal path length, providing a significant speedup for large worlds. Empirical studies combined with a feasible VLSI design estimate that path calculations on a 1000 by 1000 world could be done in approximately 110 mS worse case.

Path-finding is a fundamental problem in computer games, and its efficiency is mainly determined by the number of nodes it will expand. A* algorithm is unsuitable for path-finding on large map under limited computer sources and real-time demand, because the number of nodes it will expand grows fast with the size of the search space. HPA* can greatly improve the efficiency by generating abstract graph of the given map to memorize the map information before doing pathfinding. Through evenly partitioning the map as preprocessing, it can also reduce the influence of terrain factor on the output. As a result, it finds near optimal paths instead of optimal ones. And the evenly partition on the map doesnt consider the terrain distribution, which may still cause resource waste to some extent. In this paper, we present DT-HPA* (Hierarchical Path-Finding A* based on Decision Tree), a hierarchical path-finding approach on the map which has been divided by decision tree. This approach views each point on the map as an instance, and divides the map according to cut-points of continuous valued decision tree. The result of division is that the map is cut into some rectangular regions in different size, and retains the regions contain a kind of terrain. The experimental results show that, compared to HPA*, DT-HPA* can find more optimal paths with fewer detected nodes.KeywordsGame intelligenceHierarchical path-findingInformation entropyDecision treeDT-HPA*

In large-scale supercomputers, the interconnection network plays a key role in system performance. Network topology highly defines the performance and cost of the interconnection network. Direct topologies are sometimes used due to its reduced hardware cost, but the number of network dimensions is limited by the physical 3D space, which leads to an increase of the communication latency and a reduction of network throughput for large machines. Indirect topologies can provide better performance for large machines, but at higher hardware cost. In this paper, we propose a new family of hybrid topologies, the k-ary n-direct s-indirect, that combines the best features from both direct and indirect topologies to efficiently connect an extremely high number of processing nodes. The proposed network is an n-dimensional topology where the k nodes of each dimension are connected through a small indirect topology of s stages. This combination results in a family of topologies that provides high performance, with latency and throughput figures of merit close to indirect topologies, but at a lower hardware cost. In particular, it doubles the throughput obtained per cost unit compared with indirect topologies in most of the cases. Moreover, their fault-tolerance degree is similar to the one achieved by direct topologies built with switches with the same number of ports.

This paper investigates the solution of the optimization problem that appears in the design of double loop structured local area computer networks or interconnection networks. Double loop structure is a regular, two-connected network, designed for packet communications. The studies of degree two network connection schemes is based on the circular graphs of degree four. These graphs are regular, vertex-symmetric, and maximally connected, and such optimal graph exists for any given number of nodes. Every four of two-connected nodes consists a cluster, so cluster is a component with four input and four output link in the network. The proposed cluster network forms the optimal connection of a circular graph. We demonstrate how to construct one such network for any number of nodes and examine their network properties. The problem of routing is also addressed, and two routing rules are investigated that take advantage of the network regular structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>