Optimizing the controller IC for micro HDD process based on Taguchi methods

This paper puts forward a new structure of packaging of the RC network integrated circuit (IC) based on CSP (Chip Scale Packaging) technique, and introduces in detail the entire packaging process. Meanwhile, we have done experiments on the reliability of the packaging, and proved that RC network IC based on FCCSP (Flip Chip CSP) has a large advantage over discrete devices in the demand of high-density and high-performance circuits, and improves to a large extent in terms of reducing packaging area and parasites. Moreover, through tests on performance of the devices, it is proved that RC network IC based on CSP technique sees a less insertion loss in high frequency section.

Packaging technologies such as fan out wafer level packaging (FOWLP) and embedded chip in substrate technologies have gained a lot of attention recently from OEMs, OSATS, technology developers, and technology integrators in the integrated circuit (IC) industry as schemes for continuing wafer level chip scale package (WLCSP). Both technologies are focused on incorporating ICs into their packaging platform and on taking advantage of current process recipes and infrastructure as much as possible. However, by virtue of the new process steps and technologies required to get to 3-D packaged materials, such as through silicon vias (TSVs), wafer thinning and handling processes and requirements for alternative dielectric materials, many opportunities have arisen. Expectations are that many devices that follow a flip chip ball grid array (FCBGA) flow or WLCSP will adopt an embedded technology strategy for future generations. FOWLP has several advantages, over FCBGA and WLCSP including potential for system in package (SIP) configurations and 3-D integration, the ability to overcome pad limitation issues, and shorter interconnections and so higher electrical performance. However, to gain these advantages, requirements for processing will change due to the significant demands imposed on the materials used as permanent dielectric layers and the photoresists used in the fabrication processes. Cleaning chemistry must be designed to remove challenging films such as photoresists and residues created during other process steps; yet preserve the exposed metals such as the bond pads and Cu redistribution lines, as well as the permanent dielectrics. Device reliability and performance is heavily dependent on the proper working of all these components. The focus of this paper is to identify a manufacturable and reliable process and process window for removal of positive photoresists and residues in formation of under bump metallization (UBM) and contact pads in wafer level packaging (WLP). Our objective is to discuss a proven process that has been successfully implemented into a manufacturing environment. It has improved robustness and reliability over past-used solutions due to decreased sensitivity to moisture contamination, a significant cause of defects in many device applications.

As a consequence of the increase in data storage capacity on hard disk drives(HDDs), there is a growing need for high-density mounting technologies for printed circuit boards(PCBs) installed in them. In particular, flexible printed circuit boards(FPCs) incorporated in HDDs are facing critical issues including not only severe external restrictions but also the difficulty of mounting preamplifier integrated circuits(ICs) due to the increase in the number of pins and the size of packages. From the standpoints of both quality and productivity in HDD manufacturing, it is therefore necessary to optimize the specifications of FPCs from the conceptual design phase. We have been taking the initiative in developing high-density PCB mounting technologies. We are promoting determination of the specifications of key parts at the initial stage of the design phase and optimization of design in consideration of manufacturing quality, mounting process, and reliability, as well as reliability verification tests. These efforts are making a major contribution to the realization of high-density, high-reliability PCBs suitable. In this report, the process of design and the key technology of high-density mounting have been described.

Wafer Level Packaging (WLP) has started to shine and played a prominent role in recent years in both semiconductor and Integrated Circuit (IC) field, especially in now thriving Micro-Electro-Mechanical System (MEMS) applications on account of its distinctive operating mechanism and adaptive design variety. In this study, several crucial WLP technologies are disclosed in detail, including Wafer to Wafer (W2W) bonding, wafer level wire bonding, wafer level compound molding and lapping. Simplified and conceptual process flow of MEMS WLP and development approaches are introduced and explained. Furthermore, relevant experimental results and technology characteristics, including glass frit printing and bonding results & shear strength in W2W bonding technology, wire shift & vertical loop height & ball shear & wire pull in wafer level wire bonding technology, Thickness to Thickness Variation (TTV) & wire sweep & warpage in wafer level compound molding technology, have also been extensively demonstrated. After MEMS WLP packaging process, device performance is then determined by the difference of voltage readout with the implementation of Wafer Level Dynamic Test (WLDT) before and after Highly Accelerated Stress Test (HAST), and the wafer device yield is also presented.

Electromagnetic spectrum can be identified as a resource for the designer, as well as for the manufacturer, from two complementary points of view: first, because it is a good in great demand by many different kind of applications; second, because despite its scarce availability, it may be advantageous to use more spectrum than necessary. This is the case of Spread-Spectrum Systems, those systems in which the transmitted signal is spread over a wide frequency band, much wider, in fact, than the minimum bandwidth required to transmit the information being sent. Part I of this dissertation deals with Spread-Spectrum Clock Generators (SSCG) aiming at reducing Electro Magnetic Interference (EMI) of clock signals in integrated circuits (IC) design. In particular, the modulation of the clock and the consequent spreading of its spectrum are obtained through a random modulating signal outputted by a chaotic map, i.e. a discrete-time dynamical system showing chaotic behavior. The advantages offered by this kind of modulation are highlighted. Three different prototypes of chaos-based SSCG are presented in all their aspects: design, simulation, and post-fabrication measurements. The third one, operating at a frequency equal to 3GHz, aims at being applied to Serial ATA, standard de facto for fast data transmission to and from Hard Disk Drives. The most extreme example of spread-spectrum signalling is the emerging ultra-wideband (UWB) technology, which proposes the use of large sections of the radio spectrum at low amplitudes to transmit high-bandwidth digital data. In part II of the dissertation, two UWB applications are presented, both dealing with the advantages as well as with the challenges of a wide-band system, namely: a chaos-based sequence generation method for reducing Multiple Access Interference (MAI) in Direct Sequence UWB Wireless-Sensor-Networks (WSNs), and design and simulations of a Low-Noise Amplifier (LNA) for impulse radio UWB. This latter topic was studied during a study-abroad period in collaboration with Delft University of Technology, Delft, Netherlands.

In recent years, consumer electronics demand has been geared towards lightweight, high capacity, and high efficiency small form factor devices. These characteristics can be achieved by using three-dimensional (3D) integrated circuit (IC) technology. This study proposes a double-chip stacking structure in an embedded fan-out wafer level packaging (WLP) with double-sided interconnections. This structure consists of two or more thin dies, chip carriers, through mold vias (TMV), and interconnection structures. The thermal performance of the proposed packaging structure is examined and discussed by using finite element (FE) analysis. An FE model of the WLP is also established to compare the thermal performance of conventional WLP and the proposed packaging structure. The proposed packaging structure has a larger size and silicon carrier, which reduces its thermal resistance from 49 °C/W to 39 °C/W. By adopting the proposed design guidelines, including carrier material selection, and designating thermal vias and chip/package size ratios, FE analysis determined that the thermal performance of the proposed packaging structure can be further improved, thereby enhancing its suitability for applications with high power density.

Modern hard disk drives (HDDs) generate the head position error signal (PES) by reading special magnetic patterns called servo patterns, which are written in designated areas on the disk surface known as servo sectors, and measure the position of the head relative to the center of the data track. Servo sectors are typically created during the HDD manufacturing process and are not subsequently overwritten or erased. The process of writing servo sector patterns is known as servo track writing (STW). The accuracy and precision of the servo track writing process plays a crucial role in dictating the ultimate track density and areal storage density of the HDD. There are several mechanisms for performing servo track writing. Conventional servo track writing processes use additional sensing and positioning equipment external to the HDD. In contrast, self-servo track writing processes only use the HDD's reading and writing heads and servo system; thus avoiding many of the manufacturing cost increases and productivity losses associated with conventional servo track writing. This paper presents two novel controller synthesis methodologies for performing concentric self-servo track using a feedforward control structure. In the first methodology, it is assumed that a conventional track-following causal feedback compensator has been designed. A non-causal feedforward compensator, which utilizes the stored error signal that was created while writing the previous track, is subsequently designed using standard H8 control synthesis techniques, in order to achieve good disturbance attenuation while preventing the propagation of tracking errors from previous tracks. In the second methodology, both the track-following feedback compensator and the feedforward compensator are simultaneously designed via a mixed H 2 /H ∞ control scheme, which involves the solution of a set of linear matrix inequalities. Simulation results confirm that the two proposed control synthesis methodologies prevent error propagation from the previously written tracks and significantly improve self-servo track writing performance.

In 2014, laptops shipping with solid-state drives (SSDs) were just over 20% of the total market. There are projections that this could increase considerably over the next few years, possibly reaching over 50% of the market by 2017 [1]. This trend is driven by the decreasing costs for SSD storage capacity and the longer battery life that is possible with SSD laptops. Presently, SSDs with 256-GB capacity sell for about US$90. SSDs are still at least four-times more expensive in US$/GB than hard-disk drives (HDDs) (a 1-TB notebook HDD sells for about US$50 while a 1-TB SSD sells for about US$400) [2]. A 256-GB storage capacity is enough to hold many applications and two operating systems, with some room for data storage.

Acoustic Microscopy (AM) techniques have been utilized by labs within the microelectronics industry for failure analysis and quality assurance testing of front-end and back-end for many years. As Wafer Level Packages (WLPs) become more common and the manufacturing processes have become more standardized there has been a push toward more integrated process control system for WLPs as well. Initially standard AM lab systems were utilized with skilled operators trained to inspect and interpret the results. As volume increased improvements to the throughput were made by simplifying the operator handling of devices/parts to be screened in trays or wafer fixtures for modified laboratory systems. Eventually the increases in the volume led to operator fatigue, leading to poor interpretation of the data and miss-handling. A fully automated AM system was initially done for front-end processes, such as SOI bonded wafers, with integrated handling, AM scanning, drying and image analysis. Then there was a push for AM process control in the back-end manufacturing processes with parts handled within JEDEC trays. Since then, monitors have been added to determine and compensate for small process variations and to match systems from site to site for consistent, reliable data for total process/quality control. This presentation will discuss the development of the AM techniques and system controls that can be integrated into a WLP manufacturing process for reconstituted wafers or panels to ensure you are within control limits and providing higher yields.

In this paper, High brightness LED (light-emitting diodes) driver IC (integrated circuit) using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET (metal oxide semiconductor field effect transistor) from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. To confirm the functioning and characteristics of our proposed LED driver IC, we designed a buck converter. The LED current ripple of the designed IC is in <TEX>${\pm}5%$</TEX> and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses 1.0 <TEX>${\mu}m$</TEX> X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre (Cadence) simulation.

The current and increasing level of interest in Known Good Die (KGD) and Wafer Level Packaging (WLP) appears to be justified by the growth rate in shipments of these package types. Many analysts predict a high double to triple digit CAGR in shipments of KGD and WLP over the next several years based on increasing demand for System-In-Package (SIP) devices, handheld electronics products and personal communications gear and widespread adoption of stacked packaging. Traditional test methodology and equipment may not be optimal for production of KGD and WLP. Typical challenges encountered are wafer map transfer from inspection to test to sort, singulation (dicing) of die after testing, singulated die handling, thermal testing, equipment throughput and utilization, and optimization of manufacturing space. This paper presents a final manufacturing process flow for KGD and WLP that features optimized test handling for known-good-die, wafer-level packages and die destined for stacked packaging, allowing chipmakers to maximize product quality and profitability while meeting new package technology requirements that challenge the capabilities of conventional test handlers and wafer probers. The paper will present a case study and a comparison between the new methods and traditional processes in terms of overall equipment effectiveness and cost of ownership.

The application of organic materials used in IC advanced packaging:A review

The wafer level package (WLP) is a cost-effective solution for the electronic package, and has been increasingly applied during recent years. In this study, a new packaging technology developed based on the concepts of the WLP, the panel base package (PBP) technology, is proposed in order to further obtain the capability of signals fan-out for the fine-pitched integrated circuit (IC). In the PBP, the filler material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler and the chip surface, and the pitch of the chip side is fanned-out. The design concept and the manufacturing process of the PBP would first be described in this study. The three-dimensional finite element (FE) model is established based on the real testing sample, and the thermo-mechanical behavior of the PBP is simulated. It is found that the solder joint reliability of the PBP can be highly improved because of the applied stress buffer layer (SBL). However, the accumulated stress/strain from the coefficient of thermal expansion (CTE) mismatch may transfer to the metal lines in package. In order to enhance the robustness of the redistribution lines, the bypassed type interconnect is suggested. Moreover, the trace/pad connecting junction and the conductive via which have smooth outline are preferred to avoid the stress concentration effect.

To achieve higher storage capacities in Hard Disk Drives (HDDs), it is essential to enhance the positioning accuracy of the magnetic head, which is responsible for reading and writing data. This research aims to design an optimal high-order filter for the positioning control system to minimize the positioning error of the magnetic head in HDDs. In this study, high-order filters are constructed by sequentially combining second-order filters in parallel. A parameter optimization problem was also formulated for the high-order filter to further improve positioning accuracy, and a genetic algorithm was employed to solve it. The effectiveness of the proposed method was verified through simulations using the HDD benchmark problem developed by the IEEJ Industry Applications Society. The results confirmed that incorporating high-order filters into the HDD positioning control system significantly improved positioning accuracy.

Taguchi method was applied for designing head suspension assembly for mobile hard disk drives (HDDs). Operational shock resistance and positioning accuracy are very important. Control factors of suspension shape were selected and shock resistance and frequency response analysis by finite element method (FEM) simulation were conducted for L18 orthogonal array. New suspension design has achieved good shock resistance and frequency response function. Measurement results had good correlation with FEM simulation