Optimizing the Identification of Digital Predistorters for Improved Power Amplifier Linearization Performance

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), [Formula: see text]) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within “reasonably above” PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR [Formula: see text]50[Formula: see text]dBc, at 10[Formula: see text]W LTE modulated PA output, antenna point and PA output power of 39.5[Formula: see text]dBm.

We consider digital predistortion (DPD) for linearizing power amplifiers (PAs) of hybrid MIMO systems with subarrays. Designing such a DPD scheme is difficult because one DPD should linearize all PAs of a subarray whose beamforming coefficients are time-varying. We develop an adaptive DPD technique for each subarray based on direct learning method minimizing the sum of squared errors between the input and output signals of PAs. Use of the least mean square (LMS) Newton algorithm is proposed to adaptively control the DPD parameters. It is shown that the proposed DPD can simultaneously linearize multiple PAs in a subarray irrespective of its beamforming coefficients. Computer simulation results demonstrate that the proposed scheme can perform better than an alternative scheme that designs the DPD based on one of the PA outputs and uses the resulting DPD for all PAs of the subarray.

This paper presents a mixed-signal power amplifier (PA) with real-time hybrid Class-G and dynamic load trajectory manipulation (DLTM) operation that achieves PA efficiency enhancement into the deep power back-off (PBO) region. Moreover, we dynamically manipulate the PA load impedance trajectory that travels from the optimum output power (Pout) load impedance to the optimum efficiency load impedance during PBO, which creates PA PBO efficiency peaking. The introduced digitally intensive mixed-signal PA architecture enables precise and optimum real-time hybrid PA operation and ensures both PA output amplitude and phase accuracy. DLTM operation also extends the PA RF carrier bandwidth. A prototype PA is fully integrated in a standard 65-nm bulk CMOS process. Its load modulation network is realized by an on-chip compact transformer balun and two on-chip switch-controlled capacitors. The PA achieves +24.6-dBm (+24.4-dBm) peak P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> and 45.6% (45.8%) maximum drain efficiency (DE) at 2.4 GHz (2.8 GHz). DLTM operation extends the PA P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> and 1-dB bandwidth from 41.7% to 53.8%. By combining the real-time hybrid Class-G and DLTM operation with mixed-signal linearization, the PA delivers +17.6/+17.3-dBm (+17.3/+17-dBm) 10M-Sym/s 64QAM/256QAM at 2.4 GHz (2.8 GHz) with 27.5/26.7% (26.2/24.1%) DE, -29.2/-30.4-dB (-31.3/-31.5 dB) rms error vector magnitude (EVM), and -25.3/-25.1-dBc (-26.4/-26.1-dBc) adjacent channel leakage ratio (ACLR). The total chip area is 1.9 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Design of high-efficiency power amplifier (PA) is one of the key challenges to realize green radios, wherein digital predistortion (DPD) is deployed to reduce the PA’s power back-off and thus increase its power efficiency. As the bandwidth of the transmit signal increases, stringent requirements are posed on the DPD linearization performance with limited sampling rate and dynamic range for the analog-to-digital converter (ADC) in the DPD feedback channel. In this paper, under a fixed ADC sampling rate, novel DPD architecture is proposed to compensate for the PA nonlinearity with limited ADC dynamic range. In the feedback channel of the proposed architecture, an extra radio frequency (RF) cancellation chain is introduced to eliminate the linear component of the PA amplified signal, and thus the requirement on the ADC dynamic range can be significantly reduced. Subsequently, by accurately estimating the loop delay and attenuation of the cancellation chain, the baseband replica of the RF cancelling signal is recovered, and the original PA output signal is rebuilt to estimate the DPD coefficients. Finally, experiments show that for the long term evolution (LTE)-advanced signals, the proposed architecture can achieve an adjacent channel leakage ratio lower than −47.6 dBc, which outperforms the conventional DPD by about 3.4 dB, with the effective bits of the ADC being reduced by 4.4 and a power added efficiency of 43.8% with 7.3 dB power back-off being observed for a fabricated Doherty PA with 50-dBm saturation power.

Accurate modeling of radio-frequency power amplifier (PA) behavior is important for analyzing PA characteristics, developing novel PAs, and implementing digital predistortion (DPD) systems effectively, ultimately contributing to enhanced wireless communication performance. In this study, we examined the performance of neural-network-based PA modeling, particularly in the case of long short-term memory (LSTM)based modeling, using a relatively small training dataset. The models constructed using various configurations and learning conditions were compared to evaluate performance differences. We found that PA behavior can be modeled more accurately when residual learning and parallel LSTM structures are incorporated. In addition, incorporating both the instantaneous and smoothed amplitudes of the input signal as additional model inputs, alongside the original input signal to the modeled PA, improved performance.

In this paper, performance of class-J mode power amplifiers (PAs) is studied when a second-harmonic voltage component is added to the input node of the device. Theoretical formulations for the optimum load impedances, output power, and drain efficiency are developed for this case, and it is shown that the inclusion of a proper second-harmonic voltage at the gate node of the transistor improves the drain efficiency and output power. To check the accuracy of the theoretical analyses and the simulation results, a proof-of-concept 1-GHz 0.65-W class-J PA is fabricated in a 0.25- $\mu \text{m}$ AlGaAs-InGaAs pHEMT technology. The nonlinear gate-source capacitor ( $C_{\mathrm{ GS}}$ ) of the transistor is employed to generate the required second-harmonic voltage at the gate node. With chip dimensions of 1.57 $\times$ 1.0 mm2, the designed PA achieves a 62% power added efficiency and an 18 dB small-signal gain at 1 GHz frequency.

This article presents an assessment of the optimum mean power output of a point-absorber wave energy converter (PAWEC) in irregular wave climates. A first-order method is used to calculate the mean power spectrum of the device in waves of dissimilar spectra. JONSWAP spectra with different peak enhancement parameters are used to show the effect of energy concentration within the wave spectrum on the device mean power spectrum. A comparison of the optimum mean power output of a PAWEC in an irregular wave climate with that in an energy-equivalent regular wave climate is made to show the influence of the combination of wave spectrum and power output characteristics on the former. The principle is demonstrated by results obtained with the simulation of a PAWEC collector. An evaluation is made of the difference between the optimum mean power output of the device and the mean power output achieved using a simple, standard control method. The resulting difference in energy output with measured data from a possible site is also assessed. The implications of the results on the appraisal of device performance are considered.

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.

This paper investigates the trade-off between power amplifier (PA) nonlinearity, output power backoff (OBO), digital predistortion (DPD), and clipping and filtering (CF) in terms of energy consumption. The energy efficiency of a PA depends on the OBO of the signal and usually increases as the OBO decreases. Peak to average power ratio (PAPR) reduction methods like CF and PA linearization algorithms like DPD methods allow the use of a smaller OBO. Those algorithms show best results when used together. By studying the trade-off between the power consumed in the CF and DPD circuits versus having a larger OBO for a target bit-error rate (BER), we show that below a certain PA output power the power consumption is not reduced by decreasing the OBO. We also show that the increase in distortion noise when using DPD and CF might defeat the purpose of their use in terms of power consumption. Given the trend toward smaller cells like femtocells, requiring less output power, CF and DPD may not be required at all, leading to a simpler and power saving transmitter design.

In this paper, a method for improving feedback signal distortion over-compensation of a digital pre-distortion(DPD) system is presented. The method comprises the following steps: acquiring a distortion compensation characteristic parameter of an input signal in a forward channel of the digital pre-distortion system to form a forward channel distortion compensation lookup table(LUT), and compensating the input signal before digit-analog converter (DAC); acquiring an ideal compensation characteristic parameter of the input signal in a small closed loop without power amplification to form a feedback signal distortion compensation LUT for compensating in a feedback signal; and acquiring an ideal compensation characteristic parameter of the input signal in a big closed loop with power amplification to form a digital pre-distortion LUT dealing with power amplification non-linear distortion for compensating in the forward signal. Through the method, the over-compensation characteristic of the feedback signal can be further effectively counter balanced based on compensation to forward channel distortion to achieve the aim of improving the performance of the digital pre-distortion system.

A novel approach for power amplifier (PA) characterization suitable for single iteration digital predistorter synthesis is proposed. This approach consists of synergetic crest factor reduction and baseband digital predistortion to avoid the average power variation at the input of the PA between the characterization and linearization steps. This is achieved by bypassing the crest factor reduction block during the characterization step and by applying it concurrently with digital predistortion in the linearization step. First, the PA's behavior sensitivity to the average input power is evaluated. The limitations of conventional approaches for the PA characterization, in the context of single iteration digital predistortion, are then demonstrated. The performance of the proposed technique is validated experimentally on a 300-W peak PA. The measured improvement of the adjacent channel power ratio at the output of the linearized amplifier is 16 dBc for the conventional approach and 29 dBc for the proposed approach.

The paper presents the results of laboratory studies on influence of DC transistor operating conditions both on power amplifier (PA) linearity and effectiveness of digital predistortion procedure. The impact of DC operating conditions of 10 W GaN HEMT power amplifier on nonlinearity factors without and with digital predistortion (DPD) were investigated. The obtained results show that there is an additional improvement in adjacent channel leakage ratio (ACLR) of the order of a few dB only by an increase in the quiescent drain current of PA transistor. However, some noticeable improvement of ACLR with significant increase in PA power added efficiency (PAE) is obtained for PA with digital predistortion.

In this paper, we evaluate the effect of applying peak-to-average power ratio (PAPR) reduction and digital pre-distortion (DPD) on two types of radio frequency power amplifiers when an orthogonal frequency division multiplexing (OFDM) signal is used. The power amplifiers under test are a standard class-AB amplifier and a Doherty amplifier. The PAPR reduction methods are based on a state-of-the art convex optimization formulation and on the standard clipping and filtering technique. The DPD method consists of modeling the behavior of the power amplifier using a parallel Hammerstein model, and then extracting the inverse parameters based on the indirect learning architecture. To achieve better DPD performance, extracting the DPD parameters based on multiple-step iterations is investigated. The cases where PAPR reduction and DPD are applied separately and combined are studied and investigated. Power amplifier figures of merit are evaluated. Good performance is shown when combining both pre-processing techniques up to a certain operating point where DPD performance deteriorates due to generation of strong peaks in the signal. In addition, a difference in the power amplifier behavior is reported and analyzed.

The application of digital predistortion in base band signal is an extended method of amplifier linearization to reduce the adjacent channel interference (ACI) in those systems in which a varying envelope modulation scheme like OFDM and MQAM is used. Digital baseband predistortion is a highly cost-effective way to linearize power amplifiers (PAs), but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W-OFDM), PA memory effects can no longer be ignored. In this paper we proposed a new technique for adaptation of digital predistorter that considers memory effects in power amplifiers. This method is a combination of two techniques, memory polynomial predistortion and slope-dependent method. This new technique is validated by using a 1.9 GHz 60W LDMOS power amplifier and various signals such as 2-carrier and 3-carrier CDMA.

This paper proposes a new high efficiency power amplifier configuration injecting envelope components. The proposed configuration has the saturated power amplifier for continuous wave and the liner amplifier for extracted envelope signal from the input signal to the proposed configuration. The envelop component is extracted from the input signal, while that is injected to the input signal in the input side of the saturated power amplifier. The linear power amplifier attains the same gain of the saturated power amplifier for the extracted envelope component. At the output port of the saturated power amplifier, the extracted envelope component is injected into the output signal of the saturated power. From this process, the proposed power amplifier can achieve high efficiency amplification with acceptable the out-of-band distortion level. The calculation results show that validity of the proposed configuration. In ideal case, the proposed power amplifier can attain the efficiency of about 64% at the third-order intermodulation component to the fundamental component of -45 dBc, when the saturated efficiency of saturated power amplifier is 80%. These results show the potential of proposed configuration.