Overview of Ferroelectric Memory Devices and Reliability Aware Design Optimization

This study investigates the influence of sputtering plasma-induced damage on stochastic characteristics in HfZrO₂ (HZO)-based ferroelectric tunnel junctions (FTJs), with an emphasis on memory and neuromorphic device optimization. Variation of the sputtering plasma power during top electrode deposition introduces distinct levels of trap within the HZO layer. Low-frequency noise (LFN) spectroscopy and temperature-dependent electrical measurements confirm that higher plasma power generates additional shallow-level traps, thereby promoting Poole-Frenkel conduction while simultaneously increasing current noise magnitude. Although the resulting enhancements in on-current density and ferroelectric tunnel electroresistance (TER) ratio are beneficial for high-density memory integration, these conditions also elevate stochastic fluctuations, potentially degrading read margins and long-term endurance. Furthermore, the observed increase in stochasticity negatively affects neuromorphic inference accuracy, particularly after endurance cycling stress. These results demonstrate the critical interplay among plasma process conditions, trap density, and LFN in FTJs. By systematically engineering sputtering process parameters, we optimize the electrical performance with minimized stochastic noise. This approach provides guidelines for the development of next-generation ferroelectric-based memories and neuromorphic systems with consideration of stochasticity, where robust performance and reliability are imperative for large-scale integration.Graphical abstract

The polarization reversal in ferroelectric HfO 2 is adopted to store information in three distinct device classes – ferroelectric field effect transistors (FeFET), ferroelectric capacitors (FeCAP) and ferroelectric tunnel junctions (FTJ). Common to all three concepts is the adoption of a ferroelectric layer stack that acts either as gate dielectric in the FeFET or as the capacitor dielectric and tunneling barrier in the FeCAP or FTJ, respectively. A composite structure including an inevitably or purposefully formed dielectric layer is frequently adopted. In this work we report on the co-existence of all three memory concepts within one device structure and propose a 2T1C ferroelectric memory cell that allows the operation and comparative characterization of the trinity of ferroelectric memory devices.

Neuro-inspired deep learning algorithms have shown promising futures in artificial intelligence. Despite the remarkable progress in software-based neural networks, the traditional von-Neumann hardware architecture has suffered from limited energy efficiency while facing unprecedented large amounts of data. To meet the performance requirements of neuro-inspired computing, large-scale vector-matrix multiplication is preferred to be performed in situ, namely compute-in-memory. Non-volatile memory devices with different materials have been proposed for weight storage as synaptic devices. Among them, HfO2-based ferroelectric devices have attracted great attention because of their low energy consumption, good complementary-metal-oxide-semiconductor (CMOS) compatibility and multi-bit per cell potential. In this review, recent trends and prospects of the ferroelectric synaptic devices are surveyed. First, we present the three-terminal synaptic devices based on the ferroelectric field effect transistor (FeFET), and discuss the switching physics of the intermediate states, the back-end-of-line integration and the 3D NAND architecture design. Then, we introduce a hybrid precision synapse concept that leverages the volatile charges on the gate capacitor of the FeFET and the non-volatile polarization on the gate dielectric of the FeFET. Lastly, we review two-terminal synaptic devices using the ferroelectric tunnel junction (FTJ) and ferroelectric capacitor (FeCAP). The design margins of the crossbar array with FTJ and FeCAP analyzed.

Silicon technology has advanced through the past four decades at exponential rate both in performance and productivity. Along with the miniaturization, the power demand grew also exponentially. New technologies are studied in order to develop switches that commute faster and, in the near future, we might see an increasing number of hybrid approaches to overcome the limitations CMOS performance. The ferroelectric thin layers have been studied for memory applications, one transistor memory cell, and recently ferroelectrics have been proposed by Salahuddin and Datta as dielectric materials in transistors in order to overcome the 60mV/dec limit of the subthreshold swing (SS) in silicon Metal Ferroelectric Semiconductor Field Effect Transistors, Fe-FET. The objective of this thesis is to study the negative capacitance effect of the ferroelectrics that are integrated into the gate stack of a MOS transistor. For this purpose different Ferroelectric Field Effect Transistors (Fe-FETs) have been designed, fabricated and characterized. Due to its remarkable characteristics, like low temperature deposition, medium-k and low leakage current, vinylidene fluoride trifluorethylene, P(VDF-TrFE), an organic ferroelectric copolymer, of 100 nm and 160 nm thickness was integrated into several MOS devices. Three devices were fabricated, a metal-ferroelectric-oxide-semiconductor transistor, a metal-ferroelectric-metal-oxide-metal capacitor and a metal-ferroelectric-metal-oxide-semiconductor transistor. The internal metal was introduced in-between the two dielectrics so that the potential at that point could be probed. For the first time, subthreshold slopes as low as 48mV/dec were obtained over more than three decades of drain current. The polarization was accurately extracted and the S-shape polarization and the negative slope could be observed. The polarization presented both hysteresis and negative slope polarization. A first-order model, that can accurately characterize a Fe-FET without the negative capacitance effect, was developed and validated with the measurements. Furthermore, a model for predicting the subthreshold slope improvement in case of the negative capacitance transistor, based on the Landau's ferroelectric parameters, was presented. Among others, two possible applications of the ferroelectric transistor are highlighted, one a temperature sensor using the metal-ferroelectric-metal-oxide-semiconductor device and the other one is a Schmitt trigger based on the metal-ferroelectric-oxide-semiconductor transistor.

Edge computing requires highly energy efficient microprocessor units with embedded non-volatile memories to process data at IoT sensor nodes. Ferroelectric non-volatile memory devices are fast, low power and high endurance, and could greatly enhance energy-efficiency and allow flexibility for finer grain logic and memory. This paper will describe the basics of ferroelectric devices for both hysteretic (non-volatile memory) and negative capacitance (steep slope switch) devices, and then project how these can be used in low-power logic cell architectures and fine-grain logic-in-memory (LiM) circuits.

ABSTRACTMFMPOS (Metal, Ferroelectrics, Metal, Polysilicon, Oxide, and Silicon) one-transistor (1T) ferroelectric memory devices have been fabricated. However, the yield of 1T-memory devices is lower. We find that the main problems of 1T MFMPOS memory devices are shorts, opens, no memory window, smaller memory windows and blank. In order to solve these problems, we studied the reasons resulted in the problems. Then, the integration processes for one transistor memory device were optimized. Fabrication of nMOSFET 1T memory devices starts with shallow trench isolation (STI) on p-type Si. A gate oxide is thermally grown after p-well implantation. Phosphorus ions were implanted after polysilicon gate definition for the formation of self-aligned source, drain, and n-type floating gate. A damascene process using MOCVD PGO deposition and chemical mechanical polishing (CMP) were used to avoid etching damage. Electrodes for the ferroelectric capacitor, i.e., the floating Ir bottom electrode and Pt top electrode, are deposited by E-Beam evaporation. The area ratio of the top and floating gate electrodes is 1:1. After inter-level dielectric (ILD) deposition, contact etching stops on Pt at gate and on Si at source/drain (S/D) without difficulty because of high etch rate selectively to the Pt. Finally, the high quality 1T memory devices have been made. The one-transistor memory devices showed memory windows around 2 – 3V. The memory windows are almost saturated from operation voltage of 3V. The ratios of “on” state current to the “off” state current are closed to 8 – 9 orders. The one-transistor memory devices also show a very good memory characteristics and retention properties.

Hafnium oxide (HfO2 ) is one of the mature high-k dielectrics that has been standing strong in the memory arena over the last two decades. Its dielectric properties have been researched rigorously for the development of flash memory devices. In this review, the application of HfO2 in two main emerging nonvolatile memory technologies is surveyed, namely resistive random access memory and ferroelectric memory. How the properties of HfO2 equip the former to achieve superlative performance with high-speed reliable switching, excellent endurance, and retention is discussed. The parameters to control HfO2 domains are further discussed, which can unleash the ferroelectric properties in memory applications. Finally, the prospect of HfO2 materials in emerging applications, such as high-density memory and neuromorphic devices are examined, and the various challenges of HfO2 -based resistive random access memory and ferroelectric memory devices are addressed with a future outlook.

In this work, we adopt a low-temperature sustainable plasma treatment approach for the fabrication of ferroelectric memory devices. From our experimental results, we found that the ferroelectric polarization characteristics of HfAlOx ferroelectric device could be further improved by using low-temperature nitrogen plasma treatment on bottom TiN electrode for surface modification. The low-temperature nitrogen plasma treatment on TiN bottom electrode not only prevent electrode oxidation, but also lowers the generation of defect traps at the interface between ferroelectric HfAlOx and TiN bottom electrode during high-temperature ferroelectric annealing process. Besides, the nitrogen-treated bottom electrode also can improve bias-stress induced instability and cycling endurance of HfAlOx ferroelectric devices due to the effective suppression of randomly distributed defect traps or oxygen vacancies near the surface of bottom electrode.

This study demonstrates a new and realizable possibility of 1T-type ferroelectric random access memory devices using an all solution processing method with cellulose paper substrates. A ferroelectric poly(vinylidene fluoride–trifluoroethylene) (P(VDF-TrFE)) thin film was formed on a paper substrate with an Al electrode for the bottom-gate structure, and then a semiconducting poly(3-hexylthiophene) (P3HT) thin film was formed on the P(VDF-TrFE)/paper structure using a spin-coating technique. The fabricated ferroelectric gate field-effect transistors (FeFETs) on the cellulose paper substrates demonstrated excellent ferroelectric property with a memory window width of 20 V for a bias voltage sweep from −30 to 30 V, and the on/off ratio of the device was approximately 102. These results agree well with those of the FeFETs fabricated on a rigid Si substrate. In order to compare and check the reproducibility of the characteristics of the FeFETs on the paper substrate, it also has been attempted to make FeFETs with various channel length and width ratios were fabricated. From the measured characteristic results, it can be seen that the electrical properties of FeFETs are almost similar regardless of the substrate type. These results will lead to the emergence of printable electron devices on paper. Furthermore, these nonvolatile paper memory devices, which are fabricated by a solution processing method, are reliable, very inexpensive; have a high density; and can be fabricated easily.

Raman scattering has proven to be extremely useful for studies of phase transitions in ferroelectric materials and, in particular, as a tool to characterize soft modes [1] and features related to order-disorder phenomena [2]. The dynamical behavior of phase transitions and their sensitivity to temperature and doping can be easily elucidated by Raman scattering measurements [3–5]. The perovskite (ABO3) ferroelectric materials in thin-film form are of considerable interest, particularly for non-volatile ferroelectric random access memory and microwave devices. The ferroelectric properties depend strongly on film preparation, chemical composition and microstructures (crystal structures, orientation, grain size, domain structure, and surface roughness). Micro-Raman scattering from ferroelectric thin films provides a useful link between the phonon spectrum and the microstructure of the film.

Ferroelectrics are polar substances of either solid (crystalline or polymeric) or liquid crystals, in which inverting the external electric field can reverse the spontaneously generated electric polarization. The bistable hysteresis of ferroelectric materials offers the possibility to develop electrically switchable data storage devices. Organic non-volatile memory devices based on ferroelectricity are a promising approach towards the development of low-cost memory technology. In addition, ferroelectric memory devices generally possess the advantages of long data or operating endurance, short switching time, and low-voltage operation. In this chapter, we discuss the latest developments of ferroelectric data storage memory devices based on three main device configurations, including capacitors, field-effect transistors, and diodes. Key materials and process issues for optimizing memory performance in each device architecture and thus realizing organic ferroelectric memory are discussed. The effects of the polymer orientation, interfacial engineering, device structure, and processing parameters on the memory switching characteristics are explored systematically.

Abstract

Memory devices are an essential part of modern electronics. Efforts to move beyond the traditional “read” and “write” of digital information in volatile and non‐volatile memory devices are leading to the rapid growth of neuromorphic technology. There is a growing demand for memory devices with continuous memory states with various retention times and greater integration density with more energy‐efficient mechanisms. Two types of memory devices (i.e., non‐volatile digital memory and neuro‐synaptic devices) have been extensively investigated with emerging materials. Among numerous materials for such memory devices, in this review, the authors focus on 2D ferroelectric materials for promising memory and synaptic devices. Three types of memory devices based on 2D ferroelectric materials are classified and discussed here: 1) ferroelectric gating of semiconducting channels, 2) active ferroelectric channels, and 3) ferroelectric tunnel junction devices. It is known that atomically thin geometry competes with ferroelectricity, which can degrade the quality of the devices based on atomically thin ferroelectric materials. Various efforts to resolve the fundamental issue with emerging 2D ferroelectric materials and how they can be used as a critical element for memory and synaptic devices are surveyed.

In recent years, α-In2Se3 has attracted great attention in miniaturizing nonvolatile random memory devices because of its room temperature ferroelectricity and atomic thickness. In this work, we construct two-dimensional (2D) van der Waals (vdW) heterostructures α-In2Se3/MoS2 with different ferroelectric polarization and design a 2D graphene (Gr)/In2Se3/MoS2/Gr ferroelectric tunnel junction (FTJ) with the symmetric electrodes. Our calculations show that the band alignment of the heterostructures can be changed from type-I to type-II accompanied by the reversal of the ferroelectric polarization of In2Se3. Furthermore, the ferroelectricity persists in Gr/In2Se3/MoS2/Gr vdW FTJs, and the presence of dielectric layer MoS2 in the FTJs enables the effective modulation of the tunneling barrier by altering the ferroelectric polarization of α-In2Se3, which results in two distinct conducting states denoted as "ON" and "OFF" with a large tunneling electroresistance (TER) ratio exceeding 105%. These findings suggest the importance of ferroelectric vdW heterostructures in the design of FTJs and propose a promising route for applying the 2D ferroelectric/semiconductor heterostructures with out-of-plane polarization in high-density ferroelectric memory devices.

The recent discovery of ferroelectricity in pure ZrO2 has drawn much attention, but the information storage and processing performances of ferroelectric ZrO2-based nonvolatile devices remain open for further exploration. Here, a ZrO2 (∼8 nm)-based ferroelectric capacitor using RuO2 oxide electrodes is fabricated, and the ferroelectric orthorhombic phase evolution under electric field cycling is studied. A ferroelectric remnant polarization (2Pr) of >30 μC/cm2, leakage current density of ∼2.79 × 10-8 A/cm2 at 1 MV/cm, and estimated polarization retention of >10 years are achieved. When the ferroelectric capacitor is connected with a transistor, a memory window of ∼0.8 V and eight distinct states can be obtained in such a ferroelectric field-effect transistor (FeFET). Through the conductance manipulation of the FeFET, a high object image recognition accuracy of ∼93.32% is achieved on the basis of the CIFAR-10 dataset in the convolutional neural network (CNN) simulation, which is close to the result of ∼94.20% obtained by floating-point-based CNN software. These results demonstrate the potential of ferroelectric ZrO2 devices for nonvolatile memory and artificial neural network computing.