Package thermal resistance model dependency on equipment design

Surface mount plastic packages, including small outline transistor (SOT), small outline integrated circuit (SOIC), and plastic leaded chip carrier (PLCC), are projected to be the next generation replacement for plastic dual in-line packages (DIP's). Relative to DIP's, surface mount packages are small in size and allow higher package density on a hoard, leading to higher electrical speed for system applications. However, their small size and high density mounting in close proximity to each other make thermal management more difficult. Thermal characteristics of one class of plastic surface mount packages, namely, small outline transistor 23 and 89 packages will be addressed. The most striking feature of these packages is their small size, meaning the effective package diameter is on the same order of magnitude as the board thickness. Junction to ambient thermal resistance of these packages is less sensitive to package parameters, such as thermal conductivity of leadframe, molding compound, die bond, and chip size, than to variations in local printed circuit (PC) board temperature rise. About 80 percent of the surface mount package heat flows into the board at modest board temperatures, making the local mounting environment the greatest influence on thermal resistance. Experimental thermal resistance data for single component plastic SOT-23 and SOT-89 packages are reported. Both electrical parametric and infrared (IR) techniques were used to measure these quantities. The most noteworthy observation is that the external thermal resistance is about 2/3 of the total thermal resistance and thus controls the package's thermal behavior. The effect of density of mounting on thermal resistance of the packages is measured by IR imaging experiments. Package pitch, relative orientation of neighboring packages, and one-sided versus double-sided mountings are parameters that were varied in these experiments.

The existing iris recognition module is realized by assembly, which has large volume, high power consumption. The iris recognition module does not conform to the light and thin development trend of integrated circuits. Therefore, the industry is considering building a new iris recognition module from the bare chip and micro interconnect technology. The new module integrates a number of bare chips and passive devices in a limited space, and its thermal performance becomes more complex. It is necessary to study its performance systematically. In this paper, the thermal performance of the iris recognition module is systematically studied by the finite element method, and the influence of the thermal power of the chip, the thermal conductivity of the material and the area of PCB on the temperature and thermal resistance of the package are discussed. The results show that the thermal conductivity of chip material, the thermal power consumption of chip and the area of PCB have significant influence on packaging junction and thermal resistance of package. Package junction temperature and thermal resistance first decrease rapidly with the heat transfer coefficient of the package material, and then gradually tends to be horizontal, The effect of PCB area on the thermal performance of packaging is similar to that of the loading material, and the thermal dissipation power of the package is linearly increasing with the junction temperature of the package, and it has a horizontal linear relationship with the thermal resistance of the package.

With the continual increase in cooling demand for microprocessors, the microelectronics industry has been increasingly focused on the development of thermal solutions. Thermal Interface Material (TIM) plays a key role in reducing the thermal resistance of packaging and the thermal resistance between the electronic device and the external cooling components. Nano-TIM, a new type of thermal interface material, was developed to improve the heat dissipation of electronic devices. This paper describes work undertaken to research the reliability of Nano-TIM. Pull tests were used to investigate the shear strength of samples with Nano-TIM of different thicknesses coalesced between two PCBs with Sn coating made under different pressure. Scanning Electron Microscopy (SEM) analysis techniques were used to determine the morphology of the shear fracture section after pull tests and observe the structure of the cross section of Nano-TIM coalesced between two PCBs with Sn coating.

In this paper, package-level thermal modeling of the embedded micro-wafer-level-packaging (EMWLP) package has been performed to extract the parametric trends for thermal design guidelines of an eccentric single active die embedded alongside an integrated passive device (IPD), as shown in Fig.1 (with optional heat sink as a cooling solution). Exploratory thermal resistance modeling of an embedded two-die-stack has also been conducted. The effect of the mold compound used in the thermal models is further considered under the following parameters: mold thickness and thermal conductivity (0.4 W/mK to 2.5 W/mK). The effects of heat spreaders and heat sinks on the package thermal resistance are also studied, with due consideration paid to the above mold parameters. Furthermore, experimental characterization has been conducted to validate the package-level simulation for the single active die model, conforming to the JEDEC JESD 51-2A Thermal Measurements in Natural Convection standard. Finally, simulation results for a general system-level thermal modeling in both cellphone as well as laptop systems are also performed. Thermal management solutions for both scenarios, such as thermal vias and heat spreaders, are studied, with an optimal cooling solution proposed.

Despite the availability of various materials for chimney applications, ongoing research seeks alternatives with improved thermal and chemical resistance. Geopolymers are a promising solution, exhibiting exceptional resistance to high temperatures, fire, and aggressive chemicals. This study investigates fly ash-based lightweight geopolymer concretes that incorporate expanded clay aggregate (E.C.A.), perlite (P), and foamed geopolymer aggregate (F.G.A.). The composites were designed to ensure a density below 1200 kg/m3, reducing overall weight while maintaining necessary performance. Aggregate content ranged from 60 to 75 wt.%. Physical (density, thickness, water absorption), mechanical (flexural and compressive strength), and thermal (conductivity, resistance) properties were evaluated. F.G.A. 60 achieved a 76.8% reduction in thermal conductivity (0.1708 vs. 0.7366 W/(m·K)) and a 140.4% increase in thermal resistance (0.1642 vs. 0.0683). The F.G.A./E.C.A./P 60 mixture showed the highest compressive strength (18.069 MPa), reaching 52.7% of the reference concrete's strength, with a 32.3% lower density (1173.3 vs. 1735.0 kg/m3). Water absorption ranged from 4.9% (REF.) to 7.3% (F.G.A. 60). All samples, except F.G.A. 70 and F.G.A. 75, endured heating up to 800 °C. The F.G.A./E.C.A./P 60 composite demonstrated well-balanced performance: low thermal conductivity (0.2052 W/(m·K)), thermal resistance up to 1000 °C, flexural strength of 4.386 MPa, and compressive strength of 18.069 MPa. The results confirm that well-designed geopolymer lightweight concretes are suitable for chimney and flue pipe linings operating between 500 and 1000 °C and exposed to acidic condensates and aggressive chemicals. This study marks the initial phase of a broader project on geopolymer-based prefabricated chimney systems.

The technology of thermal analysis is very important in development of a new generation of IC package design, which aims to obtain the temperature distribution and thermal resistance of package. Most IC design engineers and package engineers have many difficulties in performing thermal analysis because they are familiar with the product structure but poor in thermal-physical modeling and FEA skills. To assist IC design engineers and package engineers to perform thermal analysis efficiently and accurately, a fully automation system (WBExcel) that has the ability to complete the whole package thermal analysis automatically has been developed based on ANSYS® Workbench and Excel. The WBExcel consits of four modules: a Package Model Information Library, an executable Wizard System, a Package Material Library and an Environment Library. The general methodology of developing this automation system is introduced. The application on PCB level analysis and component level analysis is presented and indicates the reliability and efficiency of WBExcel.

This paper presents an evaluation of the reliability of hybrid power modules using a metal matrix composite baseplate. In this study, we investigate the possible damage in the assemblies by measuring their thermal resistance. Several 2/spl times/1 power module samples including four bipolar transistors (BUX48) have been realized with the use of a vacuum bake soldering machine allowing reduction of voids in the solder joints. The test vehicles have been submitted to liquid-liquid thermal shocks (+125/spl deg/C/-55/spl deg/C). Every 250 thermal shocks, two samples were extracted in order to measure the thermal resistance. Results show that even after 2700 shocks, only a very small increase in the thermal resistance of the assemblies is observed. In comparison, modules with a copper baseplate show a strong increase in thermal resistance and fail much earlier. As a consequence, in applications where thermal cycling is involved, hybrid power modules with metal matrix composite baseplates will offer much better reliability. SEM observations conducted on cross-sectioned samples and acoustic analysis do not show the typical cracks generally observed in solder joints between the direct bonded copper substrate and the copper baseplate of aged modules.

In a previous study, it was proposed to extend the use of the junction-to-case thermal resistance, R/sub jc/, to nonisothermal packages by defining an appropriately weighted, average surface temperature based on numerically derived 'thermal influence' coefficients for each package surface (or segment) of interest. This expanded R/sub jc/ methodology is applied here to an actual plastic-leaded chip carrier (PLCC) package. Experimental data and the results of an extensive three-dimensional thermal simulation are used to establish the values of 11 sensitivity coefficients, which make it possible to determine the weighted average case temperature. The variations in the sensitivity coefficients and the accuracy of the chip temperature predictions, with the number of data sets used to determine the coefficients, are also examined. >

The high efficiency of the method of grafting functionally active polymer to fibres from aliphatic polyamides to increase their thermal and chemical resistance has been demonstrated. When the easily oxidized PDMAEM, quaternary ammonium or pyridinium bases, especially in the presence of an epoxy group in the N-alkyl radical, is contained in the grafted chains, the increase in thermal resistance and chemical stability is caused by an effect of thermooxidative cross-linking of the polymer, accompanied by a loss in its thermal plasticity.

<div class="htmlview paragraph">Power hybrids are particularly well suited for application in transportation systems because they combine a high level of functionality with low weight, size, and cost in a single electronic package. They are easy to interface with the system's logic, minimize electrical resistance and voltage overshoots, often incorporate protective circuits, allow easy fault detection and replacement, and can be largely technology transparent. An example of such a power hybrid package suitable for automotive applications was recently developed by GE and has been given the MO-55 designation by JEDEC.</div> <div class="htmlview paragraph">The power hybrid is discussed in terms of package electrical resistance, thermal resistance, both transient and steady state, and reliability, particularly corrosion protection and solder fatigue. Modeling, including finite element analysis, is applied to analyze heat flow and thermal interactions. In particular, the effect of various heatsinking and heatspreading approaches is given. Thus, the problem of choosing a heatspreader can be reduced to a simple tradeoff between chip area, the heatspreader thickness, and the heat transfer coefficient to the heat-sink. Generalized curves allow an easy assessment of heatsinking options.</div> <div class="htmlview paragraph">Highly Accelerated Stress Testing (HAST) allows a rapid assessment of corrosion resistance of the power hybrid construction approach toward damp heat under electrical bias. The thin aluminum metallization on the semiconductor chips and the bond wires are particularly vulnerable. Finally, solder fatigue is also strongly influence by the environmental conditions.</div>

In this paper, the thermal performance analysis and optimization of the package of a specific multi-heat source power device is carried out. Firstly, the finite element analysis software ANSYS Icepak is used as a tool to build a simplified model of the array type multi-power device package module. Secondly, the impact of five variable parameters on thermal performance of multi-heat source power devices is analyzed. These parameters are chip size, chip power consumption, die attach material, packaging material, package size. Finally, through the orthogonal test analysis method, the junction temperature and thermal resistance of the package are selected as the test indexes, and five parameters are selected as the orthogonal test factors to analyze the influence of the five parameters on the thermal performance. The results show that the thermal conductivity of the die attach material is most significant regardless of the package junction temperature or thermal resistance. By summarizing the influence of various factors on the thermal performance of power devices, the suggestions for optimizing the thermal performance of multi-heat source power devices are proposed. The results obtained have important guiding significance for the thermal performance optimization of power devices.

High-power emitter-coupled logic (ECL) circuits in large pin-grid array (PGA) packages must be optimized for thermal dissipation in order to operate reliably in computer applications. The steady-state and dynamic thermal characteristics of a 149-lead hermetic PGA package are studied, with emphasis on three different configurations of a finned heat sink and on two types of fillers for the epoxy heat-sink-attach adhesive. The package described has high thermal performance in an air-cooled regime. Data are presented showing thermal resistance from junction to ambient as a function of number of heatsink fins and composition of heatsink-attach epoxy. At nominal conditions, thermal resistance (junction-to-ambient) of the selected five-fin heatsink and aluminum-filled epoxy adhesive is less than 6 degrees C/W at an airflow of 500 linear feet per minute. Also discussed is the junction-to-case thermal resistance, measured as per SEMI Standard G30-86. A value of 1.2 degrees C/W was measured for the package. >

The cubic silicon carbide (3C-SiC) has been considered as a candidate structural material for several types of advanced nuclear reactors. The effects of cascade collision on thermal conductivity in symmetrical tilt grain boundary (GB) were studied by Molecular dynamics (MD) simulations. The thermal conductivity of 3C-SiC at Σ5(210)[001] GB was calculated using non-equilibrium molecular dynamics (NEMD) methods. A relatively small simulation unit was used to analyze the effect of different energies of incident PKA (primary knock-on atoms) on the thermal conductivity of 3C-SiC and to compare the results with perfect structure GB system. Finally, the vibrational density of states (VDOS) of atoms in the GB region was calculated to analyze the phonon mismatch at the interface. Calculations show that cascade collisions generated by energetic atoms will result in a decrease in thermal conductivity of the Σ5(210) GB system, but the effect varies in different regions, with a sharp decrease in thermal conductivity and an increase in thermal resistance for the intracrystalline region, while the magnitude of change in either thermal resistance or thermal conductivity is not significant in the GB region. Irradiated model shows a higher GB energy compared to the unirradiated model. For all irradiated models, lattice defects have a significant effect on the thermal conductivity of the GB system, depending on the spatial structure of the GBs. the results of the VDOS analysis suggest that an increase in the degree of atomic lattice mismatch near the interface is responsible for a further increase in the thermal resistance of the irradiated GB system.

A study of thermal cycling endurance of three different die attach adhesives by measuring the increase in thermal resistance during a thermal cycling test is discussed. Test chips were bonded to three substrates with different coefficients of thermal expansion. The thermal resistance increased with increased number of temperature cycles. A large mismatch in thermal expansion gave the fastest increase in thermal resistance. The study also revealed a significant difference in behavior between the different adhesives. >

A plastic chip-scale package (CSP) smaller than conventional packages has been developed and applied to ATM switching systems. The package uses a low-cost glass-epoxy substrate. As glass epoxy is widely used in the printed circuit boards (PCBs) of ATM switching systems, its use in the CSPs mounted on a PCB reduces the difference in thermal expansion between PCB and CSPs, thus lengthening CSP life. The power plane, ground plane, and thermal vias of the CSP are designed to offset the increased thermal resistance due to the CSP's smaller size. Simulation showed a thermal resistance for this CSP with copper layers and thermal vias of as much as 22% less than that of a CSP with no copper layers or thermal vias. A six-layer test board mounting four CSPs was used to simulate a sub-board for ATM switching systems. The thermal resistance of the two CSPs located downstream was about 10% higher than that of the two located upstream. Two CSPs were developed for two types of application-specific ICs: a bus interface controller (BIC) and a peripheral interface circuit (PIC). Both CSPs were 18 mm square with a 0.8 mm outer solder-ball pitch and 256 outer balls. These CSPs occupied areas about 87% and 68% smaller than those of a conventional pin grid array (PGA) and quad flat package (QFP) respectively. The junction temperature of both CSPs satisfied the thermal conditions. These high-performance CSPs are thus attractive for use in ATM switching systems.