Parallel algorithms for routing in nonblocking networks

A new parallel algorithm for route assignment in Benes-Clos network is studied. In packet switching systems, switch fabrics must be able to provide internally conflict-free paths simultaneously and to accommodate packets requesting for connections in real-time as they arrive at the inputs. Most known sequential route assignment algorithms, such as the looping algorithm for Benes (1962) networks or Clos (1953) networks, are designed for circuit switching systems where the switching configuration can be rearranged at a relatively low speed. Most existing parallel routing algorithms are not practical for packet switching because they either assume the set of connection requests is a full permutation or fail to deal with output contentions among the set of input packets. We develop a parallel routing algorithm by solving a set of Boolean equations which are derived from the connection requests and the symmetric structure of the Benes network. Our approach can handle both the partial permutations and the output contention problem easily. The time complexity of our algorithm is O(log/sup 2/N), where N is the network size. Furthermore, we extend the algorithm and show that it can be applied to the Clos network if the number of central modules is a power of two.

We study the connection capacity of a class of rearrangeable nonblocking (RNB) and strictly nonblocking (SNB) networks with/without crosstalk-free constraint, model their routing problems as weak or strong edge-colorings of bipartite graphs, and propose efficient routing algorithms for these networks using parallel processing techniques. This class of networks includes networks constructed from banyan networks by horizontal concatenation of extra stages and/or vertical stacking of multiple planes. We present a parallel algorithm that runs in O(lg/sup 2/ N) time for the RNB networks of complexities ranging from O(N lg N) to O(N/sup 1.5/ lg N) crosspoints and parallel algorithms that run in O(min{d* lg N, /spl radic/N}) time for the SNB networks of O(N/sup 1.5/ lg N) crosspoints, using a completely connected multiprocessor system of N processing elements. Our algorithms can be translated into algorithms with an O(lg N lg lg N) slowdown factor for the class of N-processor hypercubic networks, whose structures are no more complex than a single plane in the RNB and SNB networks considered.

In this paper, we propose three different parallel algorithms based on a state-of-the-art global router called TimberWolfSC. The parallel algorithms have been implemented by using the Message Passing Interface (MPI), and have been evaluated on a wide range of parallel platforms such as the Sun SparcCenter 1000 and the Intel Paragon. Our experimental results show good speedups and qualities from two of these parallel algorithms. We have been able to reduce runtimes of some circuits from half an hour to 5 minutes, obtained speedups of about 4.0 to 5.0 on 8 processors, with less than 2-3% degradation of quality of the solutions.

We present practical learning-based search algorithms that make it possible to automatically design key-value data structures. Our work allows searching within a space of 10100 possible designs for the optimal data structure. The input is a workload specification and the output is an abstract syntax tree which can be absorbed by modern code-generation techniques. Given the vast design space our solution is based on learning and we show that it can find the close to optimal data structure design in a matter of a few seconds.

Several parallel routing algorithms have been proposed during the last three decades. However, most algorithms have been not implemented. Therefore, the execution time and memory resources have been neither measured nor reported. This work presents two parallel routing algorithms for Omega multistage networks by using hardware assistant approach. Both algoritms have been mapped on a FPGA. The first algorithm minimizes the execution time and it is based on a priority encoder. The second one otimizes the hardware resources by using embedded FPGA memories. Omega networks are blocking and some permutations are not completely routed. Extra levels increase the routing capability by doubling the number of paths. This work evaluates the route capacity as a function of network workload, parallel networks and extra levels. Network switches with 2 and 4 inputs/outputs have been taken into account. For each connection, the first algorithm spends only two clock cycles by using the priority encoder. For the second algorithm based on memories, the number of cycles per connection ranges from 2 to 10 and the average number of cycles is around 5.

Justice-centered approaches to equitable computer science (CS) education\nframe CS learning as a means for advancing peace, antiracism, and social\njustice rather than war, empire, and corporations. However, most research in\njustice-centered approaches in CS education focus on K-12 learning\nenvironments. In this position paper, we review justice-centered approaches to\nCS education, problematize the lack of justice-centered approaches to CS in\nhigher education in particular, and describe a justice-centered approach for\nundergraduate Data Structures and Algorithms. Our approach emphasizes three\ncomponents: (1) ethics: critiques the sociopolitical values of data structure\nand algorithm design as well as the underlying logics of dominant computing\nculture; (2) identity: draws on culturally responsive-sustaining pedagogies to\nemphasize student identity as rooted in resistance to the dominant computing\nculture; and (3) political vision: ensures the rightful presence of political\nstruggles by reauthoring rights to frame CS learning as a force for social\njustice. Through a case study of this Critical Comparative Data Structures and\nAlgorithms pedagogy, we argue that justice-centered approaches to higher CS\neducation can help all computing students not only learn about the ethical\nimplications of nominally technical concepts, but also develop greater respect\nfor diverse epistemologies, cultures, and experiences surrounding computing\nthat are essential to creating the socially-just worlds we need.\n

This study aims to demonstrate the application of big data models in the evaluation of manufacturing competitiveness across different countries and economic entities. It involves analyzing algorithms and data structures, designing algorithms for evaluating manufacturing competitiveness suitable for different countries and economic entities, and providing algorithmic and theoretical support for building computer assessment models for manufacturing competitiveness in economic entities. The research adopts qualitative and quantitative methods, comparing and analyzing empirical data on manufacturing resource endowment and competitiveness in various countries, combining theoretical analysis and empirical data. By conducting a literature review and empirical research, relevant information and data are collected to establish the relationship between manufacturing resource endowment index and competitiveness. Through case studies and comparative research, this study explores the main factors affecting manufacturing competitiveness in different countries and their interrelationships. It confirms that the competitiveness of manufacturing industries in different countries is influenced by factors such as resource endowment. Further analysis quantifies the relationship between national manufacturing resource endowment and competitiveness, leading to the design of computer algorithms, data structures, and processing logic. The results demonstrate the significant role of resource endowment in manufacturing competitiveness, serving as a crucial basis for formulating comprehensive national strategies. The innovations of this study include: 1. Introducing the manufacturing resource endowment index as a key variable for evaluating competitiveness, enriching the content of competitiveness big data models. 2. Designing comprehensive data structures, algorithms, and processing logic for assessing manufacturing competitiveness from multiple perspectives. 3. In-depth analysis of the relationship and analytical methods between manufacturing strategies, resource endowment, and competitiveness, providing theoretical and model references for the design of computer big data operation platforms.

Although concurrent data structures are commonly used in practice on shared-memory machines, even the most efficient concurrent structures often lack performance theorems guaranteeing linear speedup for the enclosing parallel program. Moreover, efficient concurrent data structures are difficult to design. In contrast, parallel batched data structures do provide provable performance guarantees, since processing a batch in parallel is easier than dealing with the arbitrary asynchrony of concurrent accesses. They can limit programmability, however, since restructuring a parallel program to use batched data structure instead of concurrent data structure can often be difficult or even infeasible. This paper presents BATCHER, a scheduler that achieves the best of both worlds through the idea of implicit batching, and a corresponding general performance theorem. BATCHER takes as input (1) a dynamically multithreaded program that makes arbitrary parallel accesses to an abstract data type, and (2) an implementation of the abstract data type as a batched data structure that need not cope with concurrent accesses. BATCHER extends a randomized work-stealing scheduler and guarantees probably good performance to parallel algorithms that use these data structures. In particular, suppose a parallel algorithm has (i)T_1(i/) work, (I)T_∞(I/) span, and (I)n(I/) data-structure operations. Let (I)W(n)(I/) be the total work of data-structure operations and let (I)s(n)(I/) be the span of a size-(I)P(I/) batch. Then BATCHER executes the program in (I)O((T_1+W(n) + n s(n))/P+ s(n) T_∞)(I/) expected time on (I)P(I/) processors. For higher-cost data structures like search trees and large enough (I)n(I/), this bound becomes (I)(T_1+n\lg n)/P + T_∞lg n)(I/) provably matching the work of a sequential search tree but with nearly linear speedup, even though the data structure is accessed concurrently. The BATCHER runtime bound also readily extends to data structures with amortized bounds.

A generalized recursive circulant network(GR) is widely used in the design and implementation of local area networks and parallel processing architectures. In this paper, we investigate the routing of a message on this network, that is a key to the performance of this network. We would like to transmit maximum number of packets from a source node to a destination node simultaneously along paths on this network, where the i th packet traverses along the i th path. In order for all packets to arrive at the destination node securely, the i th path must be node-disjoint from all other paths. For construction of these paths, employing the Hamiltonian Circuit Latin Square(HCLS), a special class of (n x n) matrices, we present O(n 2 ) parallel routing algorithm on generalized recursive circulant networks.

The satisfiability(SAT) problem of large-scale propositional logic formulas has gradually become the mainstream of solutions, and some related algorithms and solvers have emerged. MiniSat is an efficient, open source solver. Its data structure, solution logic and algorithm design are also the basis of current top solvers such as Maple and Glucose. Based on the interpretation of MiniSat, this paper implements the solver bfSAT. bfSAT improves the order of clauses in the process of unit propagation, mainly for prioritizing binary clauses, making it faster to find conflict clauses, get learning clauses and backtrack. bfSAT is a solver based on algorithms and techniques implemented in MiniSat. Therefore, the solver is tested with the SAT competition 2017 benchmark data. Finally, this paper gives some optimization strategies for the world's top solvers.

Electronic circuits: by E. J. Angelo, Jr. 450 pages, diagrams, 6 × 9 in. New York, McGraw-Hill Book Co. Inc., 1958.Price, $9.00.

A range of attacks on network components, such as algorithmic denial-of-service attacks and cryptanalysis via timing attacks, are enabled by data structures for which an adversary can predict the durations of operations that he will induce on the data structure. In this paper we introduce the problem of designing data structures that confound an adversary attempting to predict the timing of future operations he induces, even if he has adaptive and exclusive access to the data structure and the timings of past operations. We also design a data structure for implementing a set (supporting membership query, insertion, and deletion) that exhibits timing unpredictability and that retains its efficiency despite adversarial attacks. To demonstrate these advantages, we develop a framework by which an adversary tracks a probability distribution on the data structure’s state based on the timings it emitted, and infers invocations to meet his attack goals.KeywordsBinary Search TreeAverage EntropyAbstract Data TypeLinked ListUnpredictable TimingThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The authors provide optimal parallel solutions to several fundamental link distance problems set in trapezoided rectilinear polygons. All parallel algorithms are deterministic, run in logarithmic time, have an optimal time-processor product and are designed to run on EREW PRAM. The authors develop techniques (e.g. rectilinear window partition) for solving link distance problems in parallel which are expected to find applications in the design of other parallel computational geometry algorithms. They employ these parallel techniques for example to compute the link diameter, link center, and central diagonal of a rectilinear polygon. Their results also imply an optimal linear-time sequential algorithm for constructing a data structure to support rectilinear link distance queries between points.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Raster graphics, while good at achieving realistic and cost-effective image generation, lacks useful (e.g. high-level) and fast (e.g. almost real-time) interaction facilities. One may try to speed up the entire classical image generation pipeline using much processing power but this would clearly lessen the advantages of raster workstations as popular, relatively inexpensive devices. This paper continues our work in restructuring the functional model (first formulated by Ingrid Carlbom) for high-performance architectures. Central to our approach is a visible concern about the underlying data structures used to represent the geometric objects. This originates from the conviction that only through careful design of appropriate graphics data structures and algorithms one can profitably map software tasks into hardware, specifically VLSI. Here we elaborate on a novel object description scheme called "pattern representation" and its envisioned usage. Our work is decidedly in contrast with several current research efforts in the area of graphics hardware where it is commonplace to simply put several processors into a cooperative effort to share the total burden, with each processor taking responsibility for part of the work.

This paper describes QUILT, a prototype geographic information system (GIS) that uses the quadtree data structure as the underlying representation for cartographic data. While QUILT contains many features typically available in a GIS, its primary purpose is to serve as a testbed for the design and testing of new data structures and algorithms for use in computer cartography. Quadtree variants for region, point and line data are implemented using the linear quadtree, organized on disk by a B-tree. QUILT provides a simple attribute attachment system which associates non-spatial data with geographic objects. The user views QUILT as an augmented LISP environment. QUILT's geographic functions include conversion of rasters to and from quadtrees; subset operations to select specified geographic objects; map editing, display, windowing, intersection and union operations; polygon expansion; and computation of geographic object properties such as the centroid, area, perimeter and bounding rectangle for sets of geog...