Parallel analysis method for a power electronic system by circuit partitioning

The pre-computation of data cubes is critical to improving the response time of on-line analytical processing (OLAP) systems and can be instrumental in accelerating data mining tasks in large data warehouses. In order to meet the need for improved performance created by growing data sizes, parallel solutions for generating the data cube are becoming increasingly important. The paper presents a parallel method for generating data cubes on a shared-nothing multiprocessor. Since no (expensive) shared disk is required, our method can be used on low cost Beowulf style clusters consisting of standard PCs with local disks connected via a data switch. Our approach uses a ROLAP representation of the data cube where views are stored as relational tables. This allows for tight integration with current relational database technology. We have implemented our parallel shared-nothing data cube generation method and evaluated it on a PC cluster, exploring relative speedup, local vs. global schedule trees, data skew, cardinality of dimensions, data dimensionality, and balance tradeoffs. For an input data set of 2000000 rows (72 Megabytes), our parallel data cube generation method achieves close to optimal speedup; generating a full data cube of /spl ap/227 million rows (5.6 Gigabytes) on a 16 processors cluster in under 6 minutes. For an input data set of 10,000,000 rows (360 Megabytes), our parallel method, running on a 16 processor PC cluster, created a data cube consisting of /spl ap/846 million rows (21.7 Gigabytes) in under 47 minutes.

Parallel processing is a key way to get good speed on difficult computer jobs thanks to how quickly computer technology is improving. Multistage Interconnection Networks (MINs) are very important in this situation because they make it easy for multiple working elements in parallel computer systems to share data and work together. The focus of this study is on how parallel methods can be used in MINs, with a focus on how these networks make it possible for nodes to communicate and process data quickly. We look at the layout and design of MINs and talk about how well they can handle apps that use a lot of data by spreading out work. We look at some of the most important parallel algorithms, like matrix multiplication, sorting, and Fast Fourier Transform (FFT), to show how they use the unique features of MINs to make computations faster and more flexible. The study also looks into the problems that come up when you try to use parallel methods, such as delay, timing issues, and load balance. It also talks about ways to deal with these problems, like route algorithms, timing methods, and fault-tolerant systems. The study shows how important parallel processing is for making high-performance computer systems work better. This helps make progress in areas like science models, big data analytics, and artificial intelligence. Through looking at how parallel algorithms and MINs work together, this study shows how parallel processing can speed up complicated calculations and make systems more efficient, leading to more advanced and scalable computing solutions.

An expression for the transfer function of a numerical integrator is derived, and is illustrated by a mapping in the complex plane. Analysing a complete system using numerical integration is shown to be equivalent to displacing the poles and zeros of its transfer function. A simple graphical method for determining this displacement is described. The implicit Euler, trapezoidal and Shichman integration formulas are considered in detail. It is shown that these are special cases of a general formula, which possesses A stability. The trapezoidal formula is the most accurate A -stable equation, although it requires a reliable method of step-length adjustment. The implicit Euler and Shichman formulas sacrifice accuracy for better stability properties, when using large step lengths.

Various fast and efficient computation techniques for a power converter simulation have been researched. According to the conventional methods, a single step size for a whole circuit is selected for the numerical integration. A real-power electronic system, however, is multirate in that its currents and voltages nonuniformly vary spatially and temporally, and its subcircuits have different transient rates. A simulation that selected an appropriate step size for each subcircuit independently would, therefore, be more efficient. Several multirate analysis techniques have already been proposed; this paper proposes a new method that divides the whole circuit into subcircuits by applying an explicit integration formula to series inductors and/or parallel capacitors, and then integrates subcircuits by applying an implicit formula with independent integration step sizes. As analysis examples, this method is applied to an ac-dc converter, a benchmark test circuit, and a dc-link inverter control system. The proposed method's effectiveness at reducing computational steps and CPU times is investigated, and its performance and efficiency are validated.

To reduce the processing time in Global Navigation Satellite System (GNSS) signal acquisition and tracking, we first propose a parallel method of signal acquisition and tracking as well as the associated software implementation in this paper. This paper applies the Message Passing Interface (MPI) and Open Multi-Processing (OpenMP) techniques for parallel computation implementation. This parallel method could put the multi-cores microprocessors to be efficiently used in GNSS signal acquisition and tracking processes. To further enhance the performance, this paper then proposes a new GNSS acquisition and tracking method, and it includes the multi-PRN code acquisition method we proposed in [Y. C. Lin and C. C. Sun, ION GNSS 2007] to reduce the acquisition processing time and a new FFT (Fast Fourier Transform)-based tracking method. This FFT-based tracking method combines the conventional tracking method and the FFT technique to track the incoming signal. Consequently, the tracking process is divided into two phases: detection and FFT-based phases. This proposed FFT-based tracking method can reduce the computational load as well. This new acquisition and tracking method will be combined with the above parallel method to gain the maximum improvement in GNSS signal acquisition and tracking. Finally, we use the real data collected by a software GNSS receiver to validate the proposed method. This paper will also conduct the comparison between the proposed method and the conventional GNSS acquisition and tracking method, and the comparison criterions are the computational load and the processing time. The experiment results of this paper show the effectiveness of this proposed approach for GNSS signal acquisition and tracking.

A Massively Parallel Spatially Resolved Stochastic Cluster Dynamics Method for Simulations of Irradiated Materials

Parallel processing is an execution of processes that make computation and calculation on many things simultaneously. In addition, parallel processing methods are applied extensively to the examination of MR imaging in treatment. As parallel computer systems become larger and faster at the present time; scientists, researchers and engineers are eventually able to find solutions to the problems in medicine, which had been taken too long to run before. Therefore, various fields including medicine and bioinformatics have already taken the advantages of parallel processing. In this review study, we deal with analyzing key concepts and eminent parallel processing methods that have been used to analyze the brain MRI images. In addition to this, we indicate great number of examples from the current literature in a comprehensive literature matrix. Based on the literature matrix that is created according to the Web of Science analysis, information graphics are presented in a comprehensive manner. As a result, parallel processing methods in brain magnetic resonance imaging offer powerful replacements to computer clusters in order to run large, disseminated solicitations.KeywordsParallel processingMagnetic resonance imagingBrainReview

This paper presents the results of a study of dynamic parallel media processing using Speculative Broadcast Loop (SBL), a speculative run-time looplevel parallelization method. Due to processing regularity, multimedia applications typically contain extensive parallelism. Subword parallelism methods are commonly used to support data parallelism between independent loop iterations in inner loops, but much of the data parallelism in media processing resides in outer loops and cannot be supported with subword parallelism. Larger-scale parallel methods are needed to enable use of the full range of data parallelism in multimedia. Because static parallel compilation methods are often unable to recognize all parallelism at compile time, a run-time method is assumed for the speculative execution of potentially parallel loops. The SBL run-time method combines SIMD parallelism with large-scale speculation for supporting data parallelism in multimedia.

The paper describes COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED results from coupling a parallel pattern simulator with a nonparallel simulator both working based on single fault propagation. Circuit partitioning and removing all feedback loops implemented into the parallel part of COMBINED result in a reduction of the number of events. In addition, the nonparallel part of COMBINED has been expanded either to detect more faults by introducing restricted symbolic fault simulation, or to reduce the number of events using PStar Algorithm which are also presented. COMBINED runs substantially faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator.

The purpose of this paper is to discuss the correctness of a method for constructing parallel processing programs from a problem description. The framework we adopt for this purpose is Equivalent Transformation Framework (ETF), which regards computation as transformation of definite clauses. In the framework, a problem's domain knowledge and a query are described in definite clauses, and its meaning is defined by a model of the set of definite clauses. Then meaning-preserving transformation rules for the query are generated. We propose a parallel processing method based on “specialization”, a part of operation in the transformations, and discuss new parallel processing method based on the specialization that maintains correctness of the computation. The specialization is generalized notion of substitution in logic programming, and it allows more rich representation. We examine the correctness of our approach based the specialization.

Reconstruction of 3-D volumetric data from C-arm CT projections is a computationally demanding task. For interventional image reconstruction, hardware optimization is mandatory. Manufacturers of medical equipment use a variety of high-performance computing (HPC) platforms, like FPGAs, graphics cards, or multi-core CPUs. A problem of this diversity is that many different frameworks and (vendor-specific) programming languages are used. Furthermore, it is costly to switch the platform, since the code has to be re-written, verified, and optimized. OpenCL, a relatively new industry standard for HPC, promises to enable portable code. Its key idea is to abstract hardware in a way that allows an efficient mapping onto real CPUs, GPUs, and other hardware. The code is compiled for the actual target by the device driver. In this work we investigated the suitability of OpenCL as a tool to write portable code that runs efficiently across different hardware. The problems chosen are back- and forward-projection, the most time-consuming parts of (iterative) reconstruction. We present results on three platforms, a multi-core CPU system and two GPUs, and compare them against manually optimized native implementations. We found that OpenCL allows to share a common framework in one language across platforms. However, considering differences in the underlying architecture, a hardware-oblivious implementation cannot be expected to deliver maximal performance. By optimizing the OpenCL code for the specific hardware we reached over 90% of native performance for both problems, back- and forward-projection, on all platforms.

This paper presents the optimized design and implementation of sparse tensor-times-dense matrix multiply (SpTTM) for CPU and GPU platforms. This primitive is a critical bottleneck in data analysis and mining applications based on tensor methods, such as the Tucker decomposition. We first design and implement sequential SpTTM to avoid explicit data transformations between a tensor and a matrix, which is the conventional approach. We further optimize SpTTM on multicore CPU and GPU systems by parallelizing, avoiding locks, and exploiting data locality. Our sequential SpTTM is up to 3.5× faster than the SpTTM from Tensor Toolbox and 1.5× over that from Cyclops Tensor Framework. Our parallel algorithms show 4.1× speedup on multicore Intel Core i7 and 18.8× speedup on NVIDIA K40c GPU over our sequential SpTTM respectively.

In this paper, we summrize the new development of hardware-acceleration techniques and a parallel conformal Finite-Difference Time-Domain (FDTD) method in computational electromagnetics engineering. We investigate the performance of a parallel conformal FDTD method on different hardware platforms, such as Intel and AMD processors, with vector-arithmetic logic unit (VALU) acceleration, a regular PC cluster, a high-performance server cluster, the use of a graphics-processing unit (GPU), and an IBM CELL processor. The FDTD method, which is parallel in nature, is one of the best candidate numerical methods for using multiple-core processors and computer clusters to efficiently simulate various electromagnetic problems. Several representative examples, such as a UWB (ultra-wideband) antenna array and reflector antennas, are employed to demonstrate the engineering applications of the parallel conformal FDTD method.

VLSI is large in scale, and complex in structure. In todays nano-VLSI, serious process variations induced by the complex nanometer integrated circuit process technology may result in severe degradation of the integrated circuit performance. These factors present ever increasing challenges for present day nano-scale VLSI design. Interconnect modeling and lithography simulations rely on numerical approaches for solving large-scale Maxwells equations, of which the computational cost is extremely high. In this paper, several massively parallel computing approaches for interconnect modeling and lithography simulation are surveyed, based on adaptive finite element theory and a parallel hierarchical grid (PHG) platform. Regarding interconnect modeling, we first review the parallel adaptive finite-element method ParAFEMCap for parasitic capacitance extraction, which achieves a parallel efficiency of 75.7\% on 1536 CPU cores. In addition, we review a hybridization of the boundary integral equation method and the random walk on spheres method (BIE-WOS) for surface charge density computations for conductors or dielectric mediums. The proposed method proves to be superior to existing methods for massively parallel computing. On a supercomputer with 5120 CPU cores, BIE-WOS can achieve almost a linear parallel efficiency. Regarding lithography simulation, we propose a parallel adaptive finite-element framework method by adopting the PHG (parallel hierarchical grid) platform and a perfectly matched anisotropy uniaxial layer to handle scattering boundary conditions.

As multi-core computers becoming the main computation force of the computer network, dynamic load balancing for parallel applications on multi-core computers needs to be studied. The paper describes a method for extending the dynamic load balancing tool to support multi-core computers. The method scales all cost function information into per CPU core unit and performs dynamic load balancing in terms of CPU cores. The parallel processes are assigned to each computer (not each CPU core) assuming that the operating system assigns the parallel processes equally among all CPU cores. The proposed tool has been successfully tested for supporting parallel CFD applications.