Parallel Text Matching Using GPGPU

Graphics processing units (GPUs) 1 have enjoyed increasing popularity in recent years, which benefits from, for example, general-purpose GPU (GPGPU) for parallel programs and new computing paradigms, such as the Internet of Things (IoT). GPUs hold great potential in providing effective solutions for big data analytics while the demands for processing large quantities of data in real time are also increasing. However, the pervasive presence of GPUs on mobile devices presents great challenges for GPGPU, mainly because GPGPU integrates a large amount of processor arrays and concurrent executing threads (up to hundreds of thousands). In particular, the root causes of performance loss in a GPGPU program can not be revealed in detail by current approaches. In this article, we propose MiC (Multi-level Characterization), a framework that comprehensively characterizes GPGPU kernels at the instruction, Basic Block (BBL), and thread levels. Specifically, we devise Instruction Vectors (IV) and Basic Blocks Vectors (BBV), a Thread Similarity Matrix (TSM), and a Divergence Flow Statistics Graph (DFSG) to profile information in each level. We use MiC to provide insights into GPGPU kernels through the characterizations of 34 kernels from popular GPGPU benchmark suites such as Compute Unified Device Architecture (CUDA) Software Development Kit (SDK), Rodinia, and Parboil. In comparison with Central Processing Unit (CPU) workloads, we conclude the key findings as follows: (1) There are comparable Instruction-Level Parallelism (ILP); (2) The BBL count is significantly smaller than CPU workloads—only 22.8 on average; (3) The dynamic instruction count per thread varies from dozens to tens of thousands and it is extremely small compared to CPU benchmarks; (4) The Pareto principle (also called 90/10 rule) does not apply to GPGPU kernels while it pervasively exists in CPU programs; (5) The loop patterns are dramatically different from those in CPU workloads; (6) The branch ratio is lower than that of CPU programs but higher than pure GPU workloads. In addition, we have also shown how TSM and DFSG are used to characterize the branch divergence in a visual way, to enable the analysis of thread behavior in GPGPU programs. In addition, we show an optimization case for a GPGPU kernel from the bottleneck identified through its characterization result, which improves 16.8% performance.

Two benchmark tests were carried out to analyze the performance of OpenFOAM-based CFD solvers using General-Purpose computing on Graphics Processing Units(GPGPU). In the present study, RapidCFD, which is an implementation of OpenFOAM capable of running most of the functions of OpenFOAM on GPUs, was used to apply GPGPU to OpenFOAM. The numerical simulations of 1) 3D lid-driven cavity incompressible flows and 2) steady flows around a motorbike were conducted on two kinds of CPU, single-GPU, and multi-GPU systems, and the computational times were analyzed. For the test of cavity flows, as the number of cells increased, the performance and the scalability of GPGPU were improved. When the number of cells was 2503, a system with 8-GPUs showed the highest performance with 42 times of speedup over a CPU system. For the test of flows around a motorbike, a system with 8-GPUs showed the highest performance with 20 times of speedup over a CPU system. For both single precision and double precision calculations, the performance improvements using GPGPU were efficient. The results demonstrate that GPGPU would be more efficient than computing on CPUs when computing large-scale flows and practical problems that require massive parallelism.

Nowadays graphics processing units (GPUs) have become popular parallel computing platforms known as General-Purpose GPU (GPGPU) computing. GPUs thereby are chosen by some security researchers as cryptographic accelerators to secure massive volumes of transactions. However, their security issues are ignored in spite of their popularity and performance. There are some possible information leakages faced with malicious attacks or even in the normal GPU computing. Our objective is to secure the confidentiality of cryptographic keys in GPU computing environments and provide easy-to-use programming with few constraints. In this paper, we propose a prototype in Linux, a system of GPGPU computing solution empowered by GPU virtualization technology, which keeps encrypted keys in guest machine to protect secret keys from leakage even in the event of full system compromise. With the API interception and redirection of CUDA, applications in Virtual Machines (VMs) can access the GPU device in a transparent way. Besides, we use virtio, a dedicated virtual I/O device, to transfer data between virtual and host machines in high performance. In our current study, we evaluate our prototype with the GPU implementation of ECC. We show that it can protect private keys of GPU cryptographic computation and it also incurs low performance penalty compared with the native environment, therefore demonstrating the prototype is secure and requires reasonable overhead.

This paper presents a method for the real-time implementation of brush stroke-based painterly rendering in a mobile environment using the General-Purpose computing on Graphics Processing Units (GPGPU). We parallelize brush search and comparison, and accelerate them using GPGPU to improve the computation time. Through this approach, a 35 times higher computational speedup was achieved for high-resolution images compared to the previous Central Processing Unit (CPU)-based painterly rendering algorithms.

The increasing adoption of graphics processing units (GPUs) for high-performance computing raises the reliability challenge, which is generally ignored in traditional GPUs. GPUs usually support thousands of parallel threads and require a sizable register file. Such large register file is highly susceptible to soft errors and power-hungry. Although ECC has been adopted to register file in modern GPUs, it causes considerable power overhead, which further increases the power stress. Thus, an energy-efficient soft-error protection mechanism is more desirable. Besides its extremely low leakage power consumption, resistive memory (e.g., spin-transfer torque RAM) is also immune to the radiation induced soft errors due to its magnetic field based storage. In this article, we propose to LEverage reSistive memory to enhance the Soft-error robustness and reduce the power consumption (LESS) of registers in the General-Purpose computing on GPUs (GPGPUs). Since resistive memory experiences longer write latency compared to SRAM, we explore the unique characteristics of GPGPU applications to obtain the win-win gains: achieving the near-full soft-error protection for the register file, and meanwhile substantially reducing the energy consumption with negligible performance degradation. Our experimental results show that LESS is able to mitigate the registers soft-error vulnerability by 86% and achieve 61% energy savings with negligible (e.g., 1%) performance degradation.

The General Purpose Graphics Processing Unit has secured a prominent position in the High-Performance Computing world due to its performance gain and programmability. Understanding the relationship between Graphics Processing Unit (GPU) power consumption and program features can aid developers in building energy-efficient sustainable applications. In this work, we propose a static analysis-based power model built using machine learning techniques. We have investigated six machine learning models across three NVIDIA GPU architectures: Kepler, Maxwell, and Volta with Random Forest, Extra Trees, Gradient Boosting, CatBoost, and XGBoost reporting favorable results. We observed that the XGBoost technique-based prediction model is the most efficient technique with an R 2 value of 0.9646 on Volta Architecture. The dataset used for these techniques includes kernels from different benchmarks suits, sizes, nature (e.g., compute-bound, memory-bound), and complexity (e.g., control divergence, memory access patterns). Experimental results suggest that the proposed solution can help developers precisely predict GPU applications power consumption using program analysis across GPU architectures. Developers can use this approach to refactor their code to build energy-efficient GPU applications.

Graphics processing units (GPUs) are providing increasingly higher performance with programmable internal processors, namely vertex processors (VPs) and fragment processors (FPs). Such newly added capabilities motivate us to perform general-purpose computation on GPUs (GPGPU) beyond graphics applications. Although VPs and FPs are connected in a pipeline, many GPGPU implementations utilize only FPs as a computational engine in the GPU. Therefore, such implementations may result in lower performance due to highly loaded FPs (as compared to VPs) being a performance bottleneck in the pipeline execution. The objective of our work is to improve the performance of GPGPU programs by eliminating this bottleneck. To achieve this, we present a code motion technique that is capable of reducing the FP workload by moving assembly instructions appropriately from the FP program to the VP program. We also present the definition of such movable instructions that do not change the I/O specification between the CPU and the GPU. The experimental results show that (1) our technique improves the performance of a Gaussian filter program with reducing execution time by approximately 40% and (2) it successfully reduces the FP workload in 10 out of 18 GPGPU programs.

Computational Fluid Dynamics (CFD) is widely used in industry and academic research to investigate complex fluid flow. The bottleneck of a realistic CFD simulation is its long simulation time. The simulation time is generally reduced by massively parallel Central Processing Unit (CPU) clusters, which are very expensive. In this paper, it is shown that the CFD simulation can be accelerated significantly by a novel hardware called General Purpose Computing on Graphical Processing Units (GPGPU). GPGPU is a cost-effective computing cluster, which uses the Compute Unified Device Architecture (CUDA) of NVIDIA devices to transform the GPU into a massively parallel processor. The paper demonstrates the faster computing ability of GPU compared to a traditional multi-core CPU. Two scenarios are simulated; one is a 2-dimensional simulation of regular wave and another one is a 3-dimensional motion of a floating ship on a regular wave. A smoothed particle hydrodynamics (SPH) based CFD solver is used for simulating the complex free-surface flow. The performance of a single GPU is compared against a commonly used 16 core CPU. For a large simulation of 6 degrees of freedom (DOF) ship motion simulation, the comparative study exhibits a speedup of more than an order of magnitude, reducing simulation time from 30 hours to about 2 hours. This indicates a CUDA enabled GPU card can be used as a cost-effective computing tool for a reliable and accurate SPH-based CFD simulation. The cost-benefit analysis of GPU over a CPU cluster is also discussed.

INTRODUCTION: The artificial bee colony (ABC) algorithm is a nature-inspired technique used for solving different optimization problems. This paper presents a multi-hive ABC algorithm for solving constrained benchmark functions of CEC2006. The CEC2006 data set contains the global benchmark functions with different design variables, number and type of constraints. OBJECTIVES: The objective of the proposed work is to design and apply the GPGPU based multi-hive ABC algorithm to solve constrained optimization problems. METHODS: The proposed approach is a multi-population coarse-grained system implemented using General Purpose Graphics Processing Unit (GPGPU). The performance of the proposed approach is compared with the serial ABC algorithm for eleven benchmark functions and results in the literature. The multi-hive ABC algorithm has multiple hives, each running separate ABC algorithm on different cores of GPGPU. RESULTS: The proposed approach provides global best solutions in significantly reduced time for all benchmark functions. The speed-up obtained is approximately 7X to 9X. The GPGPU device utilization is approximately 57% to 91%. CONCLUSION: The GPGPU based multi-hive ABC algorithm is a found good with respect to best results, speed up factor and GPU utilization to solve constrained optimization problems.

This study introduces a practical approach to implement real-time signal processing algorithms for general surveillance radar based on NVIDIA graphical processing units (GPUs). The pulse compression algorithms are implemented using compute unified device architecture (CUDA) libraries such as CUDA basic linear algebra subroutines and CUDA fast Fourier transform library, which are adopted from open source libraries and optimized for the NVIDIA GPUs. For more advanced, adaptive processing algorithms such as adaptive pulse compression, customized kernel optimization is needed and investigated. A statistical optimization approach is developed for this purpose without needing much knowledge of the physical configurations of the kernels. It was found that the kernel optimization approach can significantly improve the performance. Benchmark performance is compared with the CPU performance in terms of processing accelerations. The proposed implementation framework can be used in various radar systems including ground-based phased array radar, airborne sense and avoid radar, and aerospace surveillance radar.

The lattice Boltzmann method is a well-established numerical approach for complex fluid flow simulations. Recently, general-purpose graphics processing units (GPUs) have become available as high-performance computing resources at large scale. We report on designing and implementing a lattice Boltzmann solver for multi-GPU systems that achieves 1.79 PFLOPS performance on 16,384 GPUs. To achieve this performance, we introduce a GPU compatible version of the so-called bundle data layout and eliminate the halo sites in order to improve data access alignment. Furthermore, we make use of the possibility to overlap data transfer between the host central processing unit and the device GPU with computing on the GPU. As a benchmark case, we simulate flow in porous media and measure both strong and weak scaling performance with the emphasis being on large-scale simulations using realistic input data.

Modern General Purpose Graphic Processing Unit (GPGPU) demands a large Register File (RF), which is typically organized into multiple banks to support the massive parallelism. Although heavy banking benefits RF throughput, its associated area and energy costs with diminishing performance gains greatly limit future RF s-caling. In this paper, we propose an improved RF design with a bank stealing technique, which enables a high RF throughput with compact area. By deeply investigating the GPGPU microarchitecture, we identify the deficiency in the state-of-the-art RF designs as the bank conflict problem, while the majority of conflicts can be eliminated leveraging the fact that the highly-banked RF oftentimes experiences under-utilization. This is especially true in GPGPU where multiple ready warps are available at the scheduling stage with their operands to be wisely coordinated. Our lightweight bank stealing technique can opportunistically fill the idle banks for better operand service, and the average GPGPU performance can be improved under smaller energy budget with significant area saving, which makes it promising for sustainable RF scaling.

General Purpose Graphic Processing Unit(GPGPU) is used widely for achieving\nhigh performance or high throughput in parallel programming. This capability of\nGPGPUs is very famous in the new era and mostly used for scientific computing\nwhich requires more processing power than normal personal computers. Therefore,\nmost of the programmers, researchers and industry use this new concept for\ntheir work. However, achieving high-performance or high-throughput using GPGPUs\nare not an easy task compared with conventional programming concepts in the CPU\nside. In this research, the CPU's cache memory optimization techniques have\nbeen adopted to the GPGPU's cache memory to identify rare performance\nimprovement techniques compared to GPGPU's best practices. The cache\noptimization techniques of blocking, loop fusion, array merging and array\ntranspose were tested on GPGPUs for finding suitability of these techniques.\nFinally, we identified that some of the CPU cache optimization techniques go\nwell with the cache memory system of the GPGPU and shows performance\nimprovements while some others show the opposite effect on the GPGPUs compared\nwith the CPUs.\n

General Purpose Graphics Processing Units (GPGPUs) operate many threads concurrently, however they demand large DRAM access because of small internal memory size assigned to each thread. As a result, the power consumption in DRAM components becomes increasingly significant. We have examined a few techniques that can reduce DRAM power consumption in GPGPUs. A GPGPU simulator supporting L2 cache is used for this study. The effects of changing the memory channel organization, DRAM clock frequency, row buffer management policy, open or closed, and the L2 cache memory system are studied. Not only the total DRAM energy consumption but also that due to each DRAM operation, such as active-precharge, burst, and background, are estimated. The examined DRAM power reduction techniques bring negligible execution time changes for solving compute-bound problems, but they result in 12–27% savings of DRAM power consumption.

Both small satellites (e.g. CubeSats) and sUAS (small Unoccupied Aerial Systems) have a rapidly growing number of potential missions and can serve as platforms for a wide range of uses in science, communications, and remote sensing alone or together. The challenge is integrating these systems quickly and reliably with efficient payload operations. While much work has been completed to define and make flight control and operations available as open systems, fewer options exist for instrumentation. Some options are available for specific domains. For example, ROS (Robot Operating System) is used for many UAV (Unoccupied Aerial Vehicle) projects, but interdisciplinary use cases are non-trivial for projects that migrate payloads between UAVs and CubeSats or coordinate UAV and CubeSat joint missions. Common objectives and careful flight and ground configuration for both UAVs and CubeSats could provide a Common Instrument Stack Architecture (CISA). Many of the basic instrument integration objectives for CubeSats and sUAS share common requirements. The goal for the research architectures we are investigating, is to compare combinations of stack layers including: 1) the use of open source real-time operating systems (RTOS), such as FreeRTOS and Linux with real-time extensions, with 2) open middleware, such as ROS, cFS (core Flight System) or F Prime, and 3) image co-processing firmware. Previously developed and tested FPGA (Field Programmable Gate Array) and GP-GPU (General Purpose Graphics Processing Units) firmware for sUAS sensor networks will be integrated with CISA for performance testing. Ideally, we envision this architecture working for sensor networked flight instruments (sUAS and CubeSat) as well as ground systems (e.g. sUAS traffic management and CubeSat ground operations). To start, we are installing and evaluating the leading open-source middleware options in use for both UAVs and CubeSats integrated with our multi-core, GP-GPU, DPS, and FPGA image processing use cases to assess throughput, memory, I/O, storage, and power consumption. Our intent is to evaluate the relative merits of the underlying hardware architecture by running our prototype CISA (Common Instrument System Architecture) on off-the-shelf multi-core, GP-GPU, and FPGA SoCs (Systems-on-Chip) that have flown or are proposed for space flight, are in use with UAVs and provide best power efficiency and performance. This reference CISA stack composed of an SoC, operating system, co-processing, and middleware is hypothesized to allow future projects to migrate instrumentation and sensor payloads from UAVs to CubeSats easily and efficiently. Migration would provide continuity and scaling for research and science missions as well as joint operations. Along with objective metrics such as power and performance, the project is evaluating subjective metrics such as simplicity of integration, configuration, and interfacing common sensors.