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Paralleled Hardware Annealing for Optimal Solutions

  • Jan 1, 1995
  • Bing J Sheu +1 more
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Abstract

Optimization is an important subject in solving scientific and engineering problems. One conventional searching technique for finding the global minimum is to use gradient descent, which finds the direction for the next iteration from the gradient of the objective function. For complicated problems, the gradient descent technique often gets stuck at a local minimum where the objective function has surrounding barriers. In addition, the complexity of most combinatorial optimization problems increases dramatically with the problem size and makes it very difficult to obtain the globally optimal solution in a reasonably computational time. Complicated optimization problems could also be solved by using branch-and-bound searching method [1], or by relaxing some constraints and solving the simplified problems [2]. Several attractive methods have been reported to help the solutions of the optimization problems to escape from local minima [3 4, 5, 6, 7, 8, 9, 10]. Simulated annealing is one of the popular approaches which is widely applicable to the combinatorial optimization problems [3, 4]. Simulated annealing is a generalization of iterative improvement methods in that it accepts, with a non-zero but gradually decreasing probability, deterioration in the cost function of an optimization problem. A solution from simulated annealing is close to the global minimum within a polynomial upper bound for the computational time and is independent of the initial condition. Mean field annealing is a deterministic approximation to simulated annealing [7]. It analytically approximates the relevant Boltzmann distribution and can execute at 50 times faster than simulated annealing for some problems. The quality of the solutions produced by mean field annealing is highly dependent on the choice of the initial temperature, the cooling speed and the final temperature. So far, simulated annealing has been successfully reported in layout generation of VLSI circuits [11, 12], test pattern generation [13], integrated-circuit delay reduction [14], image segmentation [15] and noise filtering in image processing [16].

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