Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor

The Cell processor is a typical example of a heterogeneous multiprocessor on-chip architecture that uses several levels of parallelism to deliver high performance. Reducing the gap between peak performance and effective performance is the challenge for software tool developers and the application developers. Image processing and media applications are typical main stream applications. We use the Harris algorithm for detection of Points of Interest in an image as a benchmark to compare the performance of several parallel schemes on a Cell processor. The impact of the DMA controlled data transfers and the synchronizations between SPEs explains the differences between the performance of the different parallelization schemes. These results will be used to design a tool for an efficient mapping of image processing applications on multi-core architectures.

. The development of an Image Processing (IP) application is a complex activity, which can be greatly alleviated by user-friendly graphical programming environments. Our major objective is to help IP experts reuse parts of their applications. A first work towards knowledge reuse has been to propose a suitable representation of the strategies of IP experts by means of IP plans (trees of tasks, methods and tools). This paper describes the CBR module of our interactive system for the development of IP plans. After a brief presentation of the overall architecture of the system and its other modules, we explain the distinction between an IP case and an IP plan, and give the selection criteria and functions that are used for similarity calculation. The core of the CBR module is a search/adaptation algorithm, whose main steps are detailed: retrieval of suitable cases, recursive adaptation of the selected one and memorization of new cases. The system’s implementation is presently completed; its functioning is described in a session showing the kind of assistance provided by the CBR module during the development of a new IP application.

Wireless baseband processing, which is characterized by high computational complexity and high data throughput, is regarded as the most challenging issue for software radio (SR) systems, especially for the General Purpose Processor (GPP)-based SR systems. To overcome this implementation difficulty in SR systems, the multicore architecture has been proposed as the GPP-based SR platform, for example, multicore Central Processing Unit (CPU), Graphic Processing Unit (GPU) and Cell processors. In this paper, the Cell processor is considered as the core component in the GPP-based SR platform, and the channel decoding modules for convolutional, Turbo and Low-density parity-check (LDPC) codes of WiMAX systems are investigated and efficiently implemented on Cell processor. With a single Synergistic Processor Element (SPE) running at 3.2GHz, the implemented channel decoders can throughput up to 30Mbps, 1.36Mbps and 1.71Mbps for the above three codes, respectively. Moreover, the decoding modules can be easily integrated to the SR system and can provide a highly integrated SR solution.

Massively deployed inside Sony PS3 platforms, the STI Cell Broadband Engine is a multi-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). In this paper, we describe three image processing applications which we implemented on the Cell BE. We report the performance measured on one Cell blade with varying numbers of synergic processor engines enabled, and with varying application parameters. These results were compared to the results obtained on the Cell BE running a single PPE and with all 8 SPEs disabled. The results reveal the superior performance of image processing and SIMD-prone applications on the 9-core Cell BE processor over conventional RISC processors.

The purpose of this paper is to analyze the application of image processing in UAV and autopilot. UAV and autonomous driving technology are important development directions in the field of intelligent transportation and agricultural production, and image processing, as one of the core technologies supporting its perception and decision-making, plays a vital role. For UAV, in agricultural plant protection and natural disaster monitoring, the rapid evaluation and identification of farmland growth status and disaster situation can be realized through image processing technology, which provides important support for crop production and rescue work. For the automatic driving system, image processing technology can detect and track the road environment, traffic signs and pedestrians, and improve the driving safety and comfort of vehicles. However, image processing technology also faces some challenges in application, such as complex environmental conditions and real-time requirements. In the future, through the improvement of sensor technology, algorithm optimization and data sharing, the application of image processing technology in UAV and autonomous driving will be continuously improved, bringing more innovation and development opportunities for intelligent transportation and agricultural production.

This article reviews the various image processing techniques in MATLAB and also hardware implementation in FPGA using Xilinx system generator. Image processing can be termed as processing of images using mathematical operations by using various forms of signal processing techniques. The main aim of image processing is to extract important features from an image data and process it in a desired manner and to visually enhance or to statistically evaluate the desired aspect of the image. This article provides an insight into the various approaches of Digital Image processing techniques in Matlab. This article also provides an introduction to FPGA and also a step by step tutorial in handling Xilinx System Generator. The Xilinx System Generator tool is a new application in image processing and offers a friendly environment design for the processing. This tool support software simulation, but the most important is that can synthesize in FPGAs hardware, with the parallelism, robust and speed, this features are essentials in image processing. Implementation of these algorithms on a FPGA is having advantage of using large memory and embedded multipliers. Advances in FPGA technology with the development of sophisticated and efficient tools for modelling, simulation and synthesis have made FPGA a highly useful platform.

The first quarter of 2007 started as an active season for the real-time image processing community. The annual SPIE Conference on Real-Time Image Processing, which was held in San Jose, CA, highlighted recent developments in this growing branch of image processing. As one of the few regular events with its focus matching that of JRTIP, one witnessed the growth in applications of real-time image and video processing. The conference served as an effective instrument to foster the dissemination of recent results and to leverage the cohesion of the real time image processing community. The preparations for the next SPIE Conference on Real-Time Image Processing in 2008 are already progressing and its call-for-papers is included at the end of this issue. In 2007, JRTIP is going to seek involvement of more scientists in the field of real-time image and video processing. After 1 year of operation, the editors-in-chief have started to recruit additional associate editors to enlarge the expertise base of the editorial board, to solicit manuscript submissions from potential authors, and to make the reviewing process more efficient. Interested colleagues should contact the editors-in-chief expressing their Associate Editor candidature in support of one or more fields within the focus of JRTIP. In addition, they wish to encourage researchers to act as guest editors for special issues on any real-time image or video processing related topics of interest to them. It is possible to schedule two special issues in 2007, provided that a draft call-for-papers is sent to the editors-in-chief as soon as possible. The third issue of JRTIP presents four articles, two are survey papers and two are original research papers. These articles address different real-time image processing perspectives ranging from algorithmic to hardware issues. The first survey paper deals with the real-time filtering in 2D and 3D using ordered statistics that are supported by a rich set of experimental results derived from several algorithmic variations. Performance measurements are used to demonstrate the effect of noise suppression and preservation of fine image structures and to show the DSP implementation of denoising filters. The second survey paper introduces a non-invasive analysis of dynamic processes in living cells using microscopic computer vision techniques for understanding the interactions between cellular and molecular functional units and for providing novel insights into the cell biology. The third article is an original research paper covering a machine vision application involving vision-based position sensing for aerial refueling of unmanned aerial vehicles in real-time. A full image processing chain is investigated and tested in a MATLAB/Simulink soft real-time environment as well as in a Linux/RTAI hard real-time environment. The feasibility of the real-time implementation is shown using off-the-shelf commercial hardware. The fourth article is another original research paper describing a hardware architecture for real-time fractal coding for image compression. The introduced parallel hardware architecture contains units for domain M. F. Carlsohn (&) Ingenieurberatung fur Computer Vision und Bildkommunikation, Am Heiddamm 36g, 28355 Bremen, Germany e-mail: matthias.carlsohn@t-online.de

A Wavelet Transform (WT) is a mathematical technique that transforms a signal into different frequency components, each analyzed with a resolution that matches its scale. Wavelets are small waves with limited duration and they possess both time and frequency localization, which means they can capture both high-frequency and low-frequency information simultaneously. There are several types of wavelet transforms, and, depending on the application, one may be preferred to the others. For a continuous input signal, the time and scale parameters can be continuous leading to the Continuous Wavelet Transform (CWT) and Discrete wavelets. Image processing is a critical area in modern computing with applications ranging from medical imaging to remote sensing and computer vision. Traditional Fourier analysis has limitations in capturing localized features in images due to its global nature. Wavelet Transform (WT), with its multi-resolution and localized time-frequency representation, provides a powerful alternative for analysing and processing visual information. This paper presents a comprehensive overview of the theory of wavelet transforms, their mathematical foundations, and applications in image processing and signal processing, including compression of images, denoising and feature extraction from images.

As modern image and video processing applications handle increasingly higher image resolutions, the buffering requirements between communicating functional modules increase correspondingly. The performance and cost of these applications can change dramatically depending on the implementation methods for FIFO buffers and the data delivery methods between modules. This paper introduces a new FIFO hardware mapping algorithm based on pointer-based token delivery from dataflow semantics for image and video processing applications. This approach significantly improves the performance of dataflow based implementation of image and video processing systems, and allows effective prediction of changes in performance and buffer memory requirements associated with changes in image resolution. Our pointer-based token delivery method allows indirect token delivery between actors by pointers in conjunction with use of a shared memory. Each pointer references a data block stored in the shared memory. In pointer-based token delivery, a buffer can be configured to be implemented as the combination of a small, fast FIFO and a larger, relatively cheap shared memory while providing an attractive trade-off between performance and hardware cost. We present the complete semantics of our pointer-based modeling method, systematic techniques for mapping representations using these semantics into efficient implementations, and experimental results that demonstrate the performance of the proposed pointer-based techniques.

A point of interest is the characteristic of an image which can be robustly detected due to its well-defined position. The points of interest should be easily computable and are invariant to transformations in the image domain. This paper presents a novel interest point detector based on a graph centrality measure defined over the Laplacian energy of the local image network. The proposed method considers the local circular neighborhood of each pixel and associates this with an undirected graph or network. Euclidean distance is employed to connect pixels to form graph edges. The Laplacian energy of the graph will drop when a vertex is removed from it. This relative reduction indicates the significance of that vertex in the network. Graph vertices having higher values of Laplacian centrality are identified as central most nodes. This measure of pixel significance indicates the presence of interest points. The effectiveness and robustness of the proposed approach in detecting local points of high entropy values are demonstrated by the experiments conducted on standard datasets. The visual assessment of the identified interest points correlates with the coverage value calculated. Moreover, the proposed method shows stable results in the presence of geometric transformations such as rotation, viewpoint changes, and zooms. These results provide substantial evidence of the proposed interest point detector's utility in image processing applications such as image registration, object recognition, and image matching, etc.

Heterogeneous Distributed Computing (HDC) system consists of Workstations (WSs) and Personal Computers (PCs). In HDC system, each WS/PC may have different processor and performance. In order to take advantage of this diversity of processing power of a system, an effective task partitioning, scheduling, and load balancing are needed to get the optimum performance. This paper examines the effectiveness of task partitioning and scheduling strategies for image (raytracing) processing application on HDC system. The static and dynamic/Run-time Task Scheduling (RTS) strategies are shown inadequate for balancing the load of HDC system. Two adaptive tasks scheduling strategies are proposed for HDC image computing system. These adaptive strategies are: i) Master Initiate Sub-task size (MIS) strategy (based on centralized resources management approach), and ii) Worker Initiated Sub-task size (WIS) strategy (based on semi-decentralized resources management approach). The measured results show that the adaptive (MIS & WIS) strategies dramatically improve the performance of HDC raytracing system and remedy the defects of static and RTS strategies. Performances of the all investigated strategies are evaluated on manager/master and workers model of HDC system. In performance comparisons of MIS and WIS strategies, the WIS strategy shows a slightly better speedup and scalability over MIS strategy.

Signature is a special form of handwriting that contain special characters and additional forms are often used as proof of a person's identity verification. Partially legible signature, but many signatures that can not be read. However, a signature can be handled as an image so that it can be recognized using pattern recognition applications in image processing. Because the signature is the primary mechanism for authentication and authorization in legal transactions,the need for research on the development of recognition applications and automatic signature verification and efficiently increases from year to year. The method is widely used in signature recognition is a method of artificial neural network. On artificial neural networks are learning and recognition. One neural network algorithm is Learning Vector Quantization ( LVQ ) and Self Organizing Kohonen. Processes that occur in the neural network method requires a relatively long time. It is influenced by the number of data samples are used as a means of weight training update. The more and the large size of the pattern being trained, the longer the time it takes the network. LVQ is a method of training the unsupervised competitive layer will automatically learn to classify input vectors into certain classes. The classes are generated depends on the distance between the input vectors. If there are 2 input vectors are nearly as competitive layer will then classify both the input vectors into the same class. Kohonen Self Organizing Network is one of the neural network model which uses learning methods or unguided unsupervised neural network model that resembles humans. To speed up the computing process in the training and recognition is then developed an algorithm and a combination of LVQ and Self Organizing Kohonen by modifying the weight given to obtain a shorter time in the process of training and recognition.

The 16 papers in this special issue focus on adaptive sparse representation of data and applications in signal and image processing.

Image processing plays an important role in ITS. Since a traffic environment heavily depends on visual information, machine vision is a must in ITS. There are many active research and development programs applying image technologies for ITS. First of all, we need a good and clear image as an input to obtain better image processing results. For this purpose, resolution and dynamic range of an imaging device should be improved. Infrared and microwave imaging are attractive. A depth map from laser radar or microwave radar could be treated as an input to image processing. There are many applications for image processing in ITS. Typical on-board applications are: lane marker detection, obstacle detection, proximity vehicle detection, traffic signal/sign recognition, road surface monitoring, driver monitoring, etc. Roadside applications are traffic surveillance (traffic flow, travel time), incident/accident detection, license number recognition (ETC, parking lot) and parking lot surveillance.

The cellular neural/nonlinear network (CNN) is a powerful tool for image and video signal processing, as well as robotic and biological visions. The designs for CNN templates are one of the important issues for the practical applica- tions of CNNs. This paper first describes and proves the local rules of the binary Point Extract (PE) CNN introduced by Roska et al., then extends the PE CNN to a gray similar neighborhood pixel remover (SNPR) CNN. The robust design theorem of the SNPR CNN has been established, using a PE CNN and a SNPR processes several images. The results agree with theoretical predictions. In particular, combining the SNPR CNN with median filtering approach is able to re- move the salt & pepper noise in images.