Parameterized SDRAM-based content-addressable memory on field programmable gate array

Content-addressable memory (CAM) is a type of fast memory unique in its ability to perform parallel searches of stored data based on content rather than specific memory addresses. They have been used in many domains, such as networking, databases, and graph processing. Field-programmable gate arrays (FPGAs) are an attractive platform for implementing CAMs because of their low latency, reconfigurability, and energy-efficient nature. However, such implementations also face significant challenges, including high resource utilization, limited scalability, and suboptimal performance due to the extensive use of look-up tables (LUTs) and block RAMs (BRAMs). These issues stem from the inherent limitations of FPGA architectures when handling the parallel operations required by CAMs, often leading to inefficient designs that cannot meet the demands of high-speed, data-intensive applications. To address these challenges, we propose a novel configurable CAM architecture that leverages the digital signal processing (DSP) blocks available in modern FPGAs as the core resource. By utilizing DSP blocks’ data storage and logic capabilities, our approach enables configurable CAM architecture with efficient multi-query support while significantly reducing search and update latency for data-intensive applications. The DSP-based CAM architecture offers enhanced scalability, higher operating frequency, and improved performance compared to traditional LUT and BRAM-based designs. In addition, we demonstrate the effectiveness of our proposed CAM architecture with a triangle counting application on real graphs. This innovative use of DSP blocks also opens up new possibilities for highperformance, data-intensive applications on FPGAs. Our proposed design is open-sourced at: https://github.com/Xtra-Computing/DSP_CAM/.

Content-addressable memory (CAM) is a high-speed lookup memory, which searches the entire memory in parallel and provides address of the input search word. Internet of things (IoT) technology needs access control list filters, deployed using CAM, to reduce the flow of invalid data through the network. Field-programmable gate arrays (FPGAs) play an important role to provide the computational power to IoT nodes using ultra low power modern devices. CAMs are emulated in FPGAs using different memories, i.e., block RAM, distributed RAM, and flip-flops (FFs). FPGA-based CAMs have large power consumption due to the involvement of each CAM cell in parallel comparison. This work presents a bank-selective strategy for gate-based binary CAM on FPGA, which reduces the amount of comparisons and reduces power consumption on target FPGA device. For every input search key, only one bank is activated using gated-clock to compare the input key to corresponding stored rules. A sample of 512 x 36 of the proposed architecture with four banks is implemented on Xilinx Virtex-6 FPGA that consumes 42% less dynamic power compared to the best available CAM designs. Hardware resources of the proposed CAM design on target FPGA is reduced in terms of slice registers (SRs) and lookup tables (LUTs) by 7.9% and 8.8%, respectively, compared with the latest prior work.

Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in finding the address of the search key. In this paper, we present a power and resource efficient binary CAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available architectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is activated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables (LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 which improved power consumption and hardware cost by 30 and 32%, respectively, compared to the available FPGA-based CAMs.

Modern field programmable gate arrays (FPGAs) have evolved significantly in recent years and have found applications in various fields like cryptography, defense, aerospace, and many more. The integration of FPGA with highly efficient modules like DSP and block RAMs has increased the performance of FPGA significantly. This paper addresses the lesser explored feature of modern FPGA called as reconfigurable LUT (RLUT) whose content can be updated internally, even during run-time. We describe the basic functionality of RLUT and discuss its potential applications for security from both destructive and constructive point of view, highlighting the conflicted usage of RLUTs. Several use cases exploiting RLUT feature in security-critical scenarios (physical attacks related in particular) are studied in detail. The paper proposes design of stealthy hardware Trojans having zero payload overhead to highlight destructive applications which can be built using hardware Trojans. On the other hand, this paper also highlights several constructive applications based on RLUT features, starting from lightweight side-channel countermeasures to kill switch to prevent the FPGA hardware from environmental hazards and malicious attack attempts.

Modern Field Programmable Gate Arrays (FPGAs) posses small features, and have gained popularity in mission-critical systems. However, due to small FPGA features and harsh external conditions that can be faced by a mission-critical system, an FPGA chip can suffer from faults. This in turn raises the need to test an FPGA to ensure a reliable system performance. However, a mission-critical system requires that the test process should be non-intrusive, i.e., applications & FPGA regions that are not being tested remain unaffected. Hence, an online test scheme is required that not only verifies the correctness of an FPGA, but also does not degrade the performance of other, running FPGA applications. In this paper, we propose a Hardwired Network on Chip (HWNoC) as the Test Access Mechanism (TAM). Our online test scheme uses a HWNoC, to perform real-time streaming of test data that is non-intrusive to other communication traffic. Additionally, our online test scheme exhibits approx. 18 and 29 times lower spatial and temporal overheads as compared to existing schemes, respectively.

The rapid adoption of heterogeneous computing has driven the integration of Field Programmable Gate Arrays (FPGAs) into cloud datacenters and flexible System-on-Chips (SoCs). This paper shows that the integrated FPGA introduces a new security vulnerability by enabling software-based power side-channel attacks without physical proximity to a target system. We first demonstrate that an on-chip power monitor can be built on a modern FPGA using ring oscillators (ROs), and characterize its ability to observe the power consumption of other modules on the FPGA or the SoC. Then, we show that the RO-based FPGA power monitor can be used for a successful power analysis attack on an RSA cryptomodule on the same FPGA. Additionally, we show that the FPGA-based power monitor can observe the power consumption of a CPU on the same SoC, and demonstrate that the FPGA-to-CPU power side-channel attack can break timing-channel protection for a RSA program running on a CPU. This work introduces and demonstrates remote power side-channel attacks using an FPGA, showing that the common assumption that power side-channel attacks require specialized equipment and physical access to the victim hardware is not true for systems with an integrated FPGA.

A technique for implementing a Content Addressable Memory (CAM) on an FPGA is described. The CAM is highly parameterizable, allowing varying word widths, memory depths and operations to be implemented depending upon the requirements of the target application. The application of the CAM is then demonstrated by using it in the core of a network firewall application, where it is used in a pipeline IP packet detection algorithm. The firewall application is particularly useful in demonstrating the application potential of the CAM as the packet detection algorithm can be dynamically reconfigured to react to different criteria simply by altering the contents of the CAM. The result is a complete system on a chip.

Free-running ADC- and FPGA-based signal processing method for brain PET using GAPD arrays

Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanners. Our laboratory is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper two such processes, sub-clock rate pulse timing and event localization, will be discussed in detail. We show that timing performed in the FPGA can achieve a resolution that is suitable for small-animal scanners, and will outperform the analog version given a low enough sampling period for the ADC. We will also show that the position of events in the scanner can be determined in real time using a statistical positioning based algorithm.

In nuclear and high-energy physics experiments, data acquisition systems handle vast amounts of data from thousands of detectors and electronic channels, often reaching hundreds of terabits per second. While modern field programmable gate arrays (FPGAs) offer high-speed transceivers capable of processing such data, a mismatch can arise: individual analog-to-digital converters (ADCs) process lower data rates than FPGA transceivers can efficiently handle. This inefficiency leads to unnecessary usage of more powerful and expensive FPGAs, thus increasing system costs. This paper addresses this issue by proposing a link aggregator method for ADC readout. The solution integrates five universal link aggregator devices within an FPGA mezzanine card (FMC) board, enabling 1-to-1, 2-to-1, 3-to-1, or 4-to-1 multiplexing. The system optimizes FPGA resource utilization with support for up to 40 optical or copper inputs (2.5 Gbps per link) and a 10-line aggregated output (10 Gbps max) via a Vita57.1 FMC connector. A low-cost, low-power FPGA manages the mezzanine board as an intelligent standalone device. This approach significantly reduces hardware requirements and enhances cost-efficiency in high-performance data acquisition systems.

Deep Neural Networks (DNNs) are inherently computation-intensive and also power-hungry. Hardware accelerators such as Field Programmable Gate Arrays (FPGAs) are a promising solution that can satisfy these requirements for both embedded and High-Performance Computing (HPC) systems. In FPGAs, as well as CPUs and GPUs, aggressive voltage scaling below the nominal level is an effective technique for power dissipation minimization. Unfortunately, bit-flip faults start to appear as the voltage is scaled down closer to the transistor threshold due to timing issues, thus creating a resilience issue. This paper experimentally evaluates the resilience of the training phase of DNNs in the presence of voltage underscaling related faults of FPGAs, especially in on-chip memories. Toward this goal, we have experimentally evaluated the resilience of LeNet-5 and also a specially designed network for CIFAR-10 dataset with different activation functions of Rectified Linear Unit (Relu) and Hyperbolic Tangent (Tanh). We have found that modern FPGAs are robust enough in extremely low-voltage levels and that low-voltage related faults can be automatically masked within the training iterations, so there is no need for costly software- or hardware-oriented fault mitigation techniques like ECC. Approximately 10% more training iterations are needed to fill the gap in the accuracy. This observation is the result of the relatively low rate of undervolting faults, i.e., <0.1\%, measured on real FPGA fabrics. We have also increased the fault rate significantly for the LeNet-5 network by randomly generated fault injection campaigns and observed that the training accuracy starts to degrade. When the fault rate increases, the network with Tanh activation function outperforms the one with Relu in terms of accuracy, e.g., when the fault rate is 30% the accuracy difference is 4.92%.

In this work, we designed a Content Addressable Memory (CAM) in terms of Energy and power efficient using LVMOS family of IO standard on 28nm Field Programmable Gate Array (FPGA). These different IO Standards are compared with each other in terms of various power i.e. Clock power, Logic power, Signal power, IOs, Leakage power and Total power consumption to find the most power efficient one. We have analyzed our Memory at different frequencies of 1 GHz, 2 GHz, 3 GHz & 4 GHz. In this work, there is 44.46% power saving when LVCMOS_15 IO standard is used in place of LVCMOS_12 at 4 GHz operating Frequency. And there is 64.01% power saving when LVCMOS_18 is used in place of LVCMOS_12 at 1 GHz of operating frequency. For designing Content Addressable Memory, this work is done with make use of Xilinx ISE 14.4 simulator with Artix-7 FPGA.

With the rapid growth of communications via the Internet, the need for an effective firewall system which has not badly affect the overall network performances has been increased. In this paper, a Field Programmable Gate Array (FPGA) -based firewall system with high performance has been implemented using Network FPGA (NetFPGA) with Xilinx Kintex-7 XC7K325T FPGA. Based on NetFPGA reference router project, a NetFPGA-based firewall system was implemented. The hardware module performs rule matching operation using content addressable memory (CAM) for higher speed data processing. To evaluate system performance, throughput, latency, and memory utilization were measured for different cases using different tools, also the number of rules that an incoming packet is subjected to was varied to get more readings using both software and hardware features. The results showed that the designed firewall system provides better performance than traditional firewalls. System throughput was doubled times of the one with Linux-Iptables firewalls.

System security is an increasingly important design criterion for many embedded systems. These systems are often portable and more easily attacked than traditional desktop and server computing systems. Key requirements for system security include defenses against physical attacks and lightweight support in terms of area and power consumption. Our new approach to embedded system security focuses on the protection of application loading and secure application execution. During secure application loading, an encrypted application is transferred from on-board flash memory to external double data rate synchronous dynamic random access memory (DDR-SDRAM) via a microprocessor. Following application loading, the core-based security technique provides both confidentiality and authentication for data stored in a microprocessor's system memory. The benefits of our low overhead memory protection approaches are demonstrated using four applications implemented in a field-programmable gate array (FPGA) in an embedded system prototyping platform. Each application requires a collection of tasks with varying memory security requirements. The configurable security core implemented on-chip inside the FPGA with the microprocessor allows for different memory security policies for different application tasks. An average memory saving of 63% is achieved for the four applications versus a uniform security approach. The lightweight circuitry included to support application loading from flash memory adds about 10% FPGA area overhead to the processor-based system and main memory security hardware.

To meet the application needs of universal platforms such as broadband, high-frequency target recognition and tracking radar, imaging radar, etc., we design and demonstrate a multi-channel digital optical transceiver and processing microsystem. The multi-channel digital optical transceiver and processing microsystem includes a high-performance signal processing SIP (system in a package) circuit and a four-channel parallel integrated digital optical transceiver module adopting BGA980 packaging pattern, which can implement digital circuit preprocessing and high-speed optical transmission. The high-performance signal processing SIP circuit integrates one FPGA (Field Programmable Gate Array), one flash memory, one DDR3 SDRAM (Synchronous Dynamic Random-Access Memory), one EMMC (Embedded Multi Media Card), one ADC (Analog-to-Digital Converter) and one DAC (Digital-to-Analog Converter). The four-channel parallel integrated digital optical transceiver consists of transmitting end and receiving end, with a single channel optical transmission rate of 10.3125Gbps. The transmitting end of the module is composed of an VCSEL array laser and its driven control circuit, while the receiving end is composed of a detector array and TIA (Trans- Impedance Amplifier) circuit. The module adopts LCC48 surface mount packaging form and transmits data through flat ribbon fiber bundles via MT type interface. The high-performance signal processing SIP circuit and the four-channel parallel integrated digital optical transceiver module achieve control and data transmission through the GTX (Gigabyte Transceiver) interface in the FPGA chip. We demonstrate a transmission loop experiment to test the transmission rate and transmission quality, using the IBERT (Integrated Bit Error Ratio Tester) module in the vivado software. When the link rate parameter in FPGA is set to 6.25Gbps, the result in vivado shows that the link is normal and the eye diagram opens well. The measured bit error ratios of the transmitting end and the receiving end are 1.86×10^-12 and 2.20×10^-12 respectively. This type of microsystem has advantages of anti-interference, broadband, high-frequency, small size, and high transmission rate, which plays an important role in fields such as electronic antagonism.