Parameterized transient thermal behavioral modeling for chip multiprocessors

In this paper, we study a new architecture level thermal modeling problem from behavioral modeling perspective to address the emerging thermal related analysis and optimization problems for high-performance quad-core microprocessor designs. We propose a new approach to build the thermal behavioral models by using transfer function matrix from the measured thermal and power information at the architecture level. The new method builds behavioral thermal model using generalized pencil-of-function (GPOF) method, which was developed in the communication community to build the rational modeling from the measured data of real-time systems. To effectively model transient temperature changes, we propose two new schemes to improve the GPOF. First we apply logarithmic-scale sampling instead of traditional linear sampling to better capture the temperature changing characteristics. Second, we modify the extracted thermal impulse response such that the extracted poles from GPOF are guaranteed to be stable without accuracy loss. Experimental results on a practical quad-core microprocessor show that generated thermal behavioral models match the measured data very well.

In this paper, package-level thermal modeling of the embedded micro-wafer-level-packaging (EMWLP) package has been performed to extract the parametric trends for thermal design guidelines of an eccentric single active die embedded alongside an integrated passive device (IPD), as shown in Fig.1 (with optional heat sink as a cooling solution). Exploratory thermal resistance modeling of an embedded two-die-stack has also been conducted. The effect of the mold compound used in the thermal models is further considered under the following parameters: mold thickness and thermal conductivity (0.4 W/mK to 2.5 W/mK). The effects of heat spreaders and heat sinks on the package thermal resistance are also studied, with due consideration paid to the above mold parameters. Furthermore, experimental characterization has been conducted to validate the package-level simulation for the single active die model, conforming to the JEDEC JESD 51-2A Thermal Measurements in Natural Convection standard. Finally, simulation results for a general system-level thermal modeling in both cellphone as well as laptop systems are also performed. Thermal management solutions for both scenarios, such as thermal vias and heat spreaders, are studied, with an optimal cooling solution proposed.

Enhancement of waste heat recovery from vertical chimney via thermoelectric generators by heat spreader

Photonics Integrated Circuits (PICs), a feature of contemporary optical communications technologies, can represent a stringent packaging challenge, particularly in terms of their requirements for thermal control. Devices such as laser arrays can demonstrate tight temperature limits, sub-ambient operating temperatures, moderate heat loads but high device-level heat fluxes. A key feature of many hybrid PICs is a multi-layer substrate which offers mechanical support, electrical interconnection and heat spreading for the devices that it carries; such substrates are typically mounted on a thermoelectric module (TEM) to achieve thermal control. This paper considers two thermal challenges associated with such PICs, in order to ensure their efficient operation: the requirement for aggressive heat sinking; and the imperative of adequate heat spreading within the substrate on the temperature controlled side of the TEM. To this end, a closed-form electrothermal model is developed for a representative PIC which captures the conductive heat transfer within the substrate, coupled with a constitutive representation of the TEM and its heat sink. An example of a laser array PIC is considered in order to illustrate the importance of heat sinking and spreading. This paper represents some initial results of an extensive programme of work on packaging-related aspects of next-generation PICs.

Thermal interface materials (TIMs), consisting of high conductivity filler particles dispersed in a polymer matrix, are used in thermal management of electronics to bridge the gap between the heat generating components and the heat spreader or heat sink. Without TIMs, there is imperfect contact at the interface, resulting in detrimental chip performance and elevated temperatures that can ultimately lead to failure of the chip. In commercial applications, TIMs are dispensed on the chip, heat spreader, or the heat sink using a nozzle via an automated process. The TIM is then squeezed into a thin layer over the substrate by the alternate component (i.e., the device, heat spreader, or the heat sink), often followed by curing (e.g., at elevated temperature) to form a rigid bond. During squeezing, the particle-laden TIM generally exhibits non-Newtonian behavior and, after squeezing, the particle spatial distribution may be non-uniform. The flow behavior depends on dispense pattern (e.g., dots, lines, star patterns), parameters of the squeezing process (e.g., force and squeezing rate), and the TIM composition (e.g., particle shape, size distribution, volume fraction, and matrix composition). The velocity and applied pressure during squeezing significantly impacts the achievable bond line thickness (BLT) and the particle spatial distribution, which can cause the thermal performance of the TIM to deviate from the vendor-specified thermal characteristics. In practice, the maximum allowable squeeze pressure, which impacts the final BLT, is limited by potential mechanical failure of packaged electronics. There are open questions regarding the effect of squeezing on particle rearrangement and its effect on thermal conduction within the particle network. In this work, X-ray micro-computed tomography (XRCT) is used to measure the spatial distribution of particles in the TIM after (a) dispensing and (b) squeezing processes. A mock TIM with a target of 30 vol% copper microspheres (median diameter 114 μm) is created by handmixing the particles with a UV-curable epoxy. Microstructural features such as the average particle volume fraction, coordination number and radial distribution function (RDF) are computed to gain insights into the particle spatial arrangement in the TIM.

Improved thermal management is needed to increase the power density of electronic and more effectively cool electronic enclosures that are envisioned in future aircraft, spacecraft and surface ships. Typically, heat exchanger cores must increase in size to more effectively dissipate increased heat loads, this would be impossible in many cases, thus improved heat exchanger cores will be required. In this Phase I investigation, MRi aimed to demonstrate improved thermal management using graphite foam (Gr-foam) core heat exchangers. The proposed design was to combine Gr-foams from POCO with MRi's innovative low temperature, active metal joining process (S-Bond{trademark}) to bond Gr-foam to aluminum, copper and aluminum/SiC composite faceplates. The results were very favorable, so a Phase II SBIR with the MDA was initiated. This had primarily 5 tasks: (1) bonding, (2) thermal modeling, (3) cooling chip scale packages, (4) evaporative cooling techniques and (5) IGBT cold plate development. The bonding tests showed that the ''reflow'' technique with S-Bond{reg_sign}-220 resulted in the best and most consistent bond. Then, thermal modeling was used to design different chip scale packages and IGBT cold plates. These designs were used to fabricate many finned graphite foam heat sinks specifically for two standard type IC packages, the 423 and 478 pin chips. These results demonstrated several advantages with the foam. First, the heat sinks with the foam were lighter than the copper/aluminum sinks used as standards. The sinks for the 423 design made from foam were not as good as the standard sinks. However, the sinks made from foam for the 478 pin chips were better than the standard heat sinks used today. However, this improvement was marginal (in the 10-20% better regime). However, another important note was that the epoxy bonding technique resulted in heat sinks with similar results as that with the S-bond{reg_sign}, slightly worse than the S-bond{reg_sign}, but still better than the standard heat sinks. Next, work with evaporative cooling techniques, such as heat pipes, demonstrated some unique behavior with the foam that is not seen with standard wick materials. This was that as the thickness of the foam increased, the performance got better, where with standard wick materials, as the thickness increases, the performance decreases. This is yet to be completely explained. Last, the designs from the thermal model were used to fabricate a series of cold plates with the graphite foam and compare them to similar designs using high performance folded fin aluminum sinks (considered standard in the industry). It was shown that by corrugating the foam parallel to fluid flow, the pressure drop can be reduced significantly while maintaining the same heat transfer as that in the folded fin heat sink. In fact, the results show that the graphite foam heat sink can utilized 5% the pumping power as that required with the folded fin aluminum heat sink, yet remove the same amount of heat.

Under the complex operational environment of the antimissile operation, the application of Systems Modeling Language (SysML) parametric model in weapon system effectiveness evaluation is explored. The function of parametric graph model, the construction process of the model and the optimization method of the model are researched. Using feedback mechanism to collect, collate and calculate the parameters of the model, and realize the leap from the index relationship description to the calculation of the index. Finally, the feasibility and effectiveness of the proposed method is verified by using the system of antimissile weapon system as an example.

High-heat-flux removal is critical for the next-generation electronic devices to reliably operate within their temperature limits. A large portion of the thermal resistance in a traditional chip package is caused by thermal resistances at interfaces between the device, heat spreaders, and the heat sink; embedding the heat sink directly into the heat-generating device can eliminate these interface resistances and drastically reduce the overall thermal resistance. Microfluidic cooling within the embedded heat sink improves the heat dissipation, with two-phase operation offering the potential for dissipation of very high heat fluxes while maintaining moderate chip temperatures. To enable multichip stacking and other heterogeneous packaging approaches, it is important to densely integrate all fluid flow paths into the device; volumetric heat dissipation emerges as a performance metric in this new heat sinking paradigm. In this paper, a compact hierarchical manifold microchannel design is presented that utilizes an integrated multilevel manifold distributor to feed coolant to an array of microchannel heat sinks. The flow features in the manifold layers and microchannels are fabricated in silicon wafers using deep reactive-ion etching. The heat source is simulated via Joule heating using thin-film platinum heaters. The on-chip spatial temperature measurements are made using four-wire resistance temperature detectors. The individual manifold layers and the microchannel-bearing wafers are diced and bonded into a sealed stack via thermocompression bonding using gold layers at the mating surfaces. Thermal and hydrodynamic testing is performed by pumping the dielectric fluid HFE-7100 through the device at a known flow rate, temperature, and pressure at different levels of chip heat input. A volumetric heat density of up to 2870 W/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> is dissipated at a chip temperature less than 112 °C and microchannel pressure drop less than 27 kPa. The overall pressure drop is governed by flowing through the manifold, rather than the microchannels, in this compact heat sink that occupies envelope of 5 mm × 5 mm × 2.3 mm including all the functional flow features.

This paper presents the results of thermal performance and mechanical reliability co-design of flip chip devices by a comprehensive evaluation of package structure and material effects. The study provided valuable insights that can assist to identify potential package solutions and enhancement options by considering process, materials, thermal performance and mechanical reliability. With concurrent thermal and mechanical analysis, the thermal trends obtained from this study can be used to enhance the selection of thermal options and the reliability insights gained allowed further mechanical optimizations to identified solutions. The study evaluates both the larger sized FC-BGA and smaller sized FC-CSP using selected production, development and potential devices. A total of 6 FC-BGA and 5 FC-CSP test vehicles were selected for the study. The UTAC-patented XP (eXtra Performance) embedded heat spreader was also assessed and benchmarked against the other test vehicles. Thermal performance analysis, detailed package level stress and warpage analysis were conducted for all the identified test vehicles. For both FC-BGA and FC-CSP devices, analysis results showed that the bare die structure has the highest warpage and highest junction-to-ambient thermal resistance. The addition of mold compound is able to improve warpage for small die FC-BGA packages. However, mold compound results in insignificant warpage improvements when die-topackage ratio is large, such as in the FC-CSP. Concurrent thermal analysis shows that mold compound slightly enhances the thermal performance of both FC-BGA and FC-CSP devices under no/low wind velocities. Heat spreaders or heat sinks are comparatively more effective thermal enhancement solutions. The effects of heat spreaders were analyzed using several different package structures. Other than the thermal benefits reaped, heat spreaders brought about significant warpage control. Especially in the case of XP, the combined effect of the mold compound and the embedded heat spreader remarkably reduced warpage even in package with large dieto-package ratio. However, stress analysis showed a 10-25% increase in die stress for both small and large die packages when the heat spreader is used. With the recent interest and migration to the use of moldable underfill material (MUF), its performance was also benchmarked against the conventional capillary underfill (CUF) and mold compound. Thermal analysis results shows that MUF results in minor thermal enhancements compared to the capillary underfill (CUF). Mechanical analysis results showed that the MUF improves package coplanarity when the package exhibited smiling warpage behaviour at room temperature. The shift in critical die and underfill stresses was also observed with the change in material set. The thermal performance and mechanical reliability costudy adopted a holistic approach that obtained the trends and insights learnt that enabled informed choices to be made in materials selection and identification of potential packages. The approach and the insights obtained are thus presented in this paper.

The use of a micro heat sink is an effective means of solving the problem of high-power chip heat dissipation. Diamond/Cu composites exhibit high thermal conductivity and a linear thermal expansion coefficient that is compatible with semiconductor materials, rendering them ideal micro heat sink materials. The aim of this study was to fabricate diamond/Cu and Cu separately as heat sinks and subject them to flow boiling heat transfer experiments. The results indicate that the diamond/Cu heat sink displayed a decrease in wall superheat of 10.2–14.5 °C and an improvement in heat transfer coefficient of 38–51% compared with the Cu heat sink under identical heat fluxes. The heat sink also exhibits enhanced thermal uniformity. Secondary diamond particles are incorporated into the gaps of the main diamonds, thereby constructing a three-dimensional heat conduction network within the composite material. The diamond network enhances the internal heat flux of the material while also creating more nucleation sites on the surface. These increase the boiling intensity of the diamond/Cu heat sink, leading to better heat transfer performance. By combining the transient thermal model with computational fluid dynamics, a heat transfer model based on the diamond/Cu heat sink is proposed. The efficient heat dissipation capability of diamond/Cu heat sinks can lower the working temperature of microelectronic devices, thereby improving device performance and reliability during operation.

This study describes a thermal design method of forced convection cooling in high-density packaging electronic equipment for upstream design processes by flow and thermal resistance network analysis. Forced convection cooling by combining fans and heat sinks is the most standard strategy for dissipating heat from electronic equipment. In recent years, the thermal design of electronic equipment becomes more critical, and fast thermal design is required due to the rapid development of final products. We have been developing the flow and thermal resistance network analysis as the quick thermal design method for electronic equipment. However, an accurate prediction of forced convection cooling performance by finned heat sinks mounted in high-density packaging electronic equipment is generally tricky. Some bypasses, which are clearances between the heat sinks and enclosure walls or other components, exist around the heat sinks. Therefore, a flow rate distribution between the heat sink fins and the bypasses should be predicted. Many researchers have investigated hydrodynamic characteristics and heat transfer characteristics of finned heat sinks. However, many previous studies have been conducted on the finned heat sink performance when there are no bypasses. In order to achieve an optimum design of the finned heat sinks in the upstream configuration regardless of the heat sink dimensions, a systematic database of hydrodynamic characteristics and heat transfer characteristics of the finned heat sinks with bypasses should be investigated. This paper discusses the development of function models of pressure drop, flow rate distribution, and heat transfer of the finned heat sinks with the bypasses for the resistance network analysis through experiments and CFD analysis. Several types of finned heat sinks with 40 mm in width and 80 mm in length were prepared, and these were mounted in a rectangular enclosure with 45 mm in width and height. First, the pressure drop characteristic around the heat sink was investigated. In addition, the flow rate distribution between the heat sink and the bypass was evaluated separately. A flow branching coefficient was developed to predict the flow rate distribution around the heat sink combined with the pressure drop coefficient. Using the developed flow branching coefficient, the flow and thermal resistance network model around the finned heat sink was developed. The results from the proposed resistance network model showed good agreement with those from the experiment.

PurposeThe purpose of this paper is to optimize the configuration sizes of micro‐channel cooling heat sink using the thermal resistance network model. The optimized micro‐channel heat sink is simulated by computational fluid dynamics method, and the total thermal resistance is calculated to compare with that of thermal resistance network model.Design/methodology/approachTaking the thermal resistance and the pressure drop as goal functions, a multi‐objective optimization model was proposed for the micro‐channel cooling heat sink based on the thermal resistance net work model. The Sequential Quadratic Programming procedure was used to do the optimization design of the structure size of the micro‐channel. The optimized micro‐channel heat sink was numerically simulated by computational fluid dynamics (CFD) software.FindingsFor the heat sink to cool a chip with the sizes of L × W = 2.5 mm × 2.5 mm and the power of 8 W, the optimized width and height of the micro‐channel are 154 μm and 1,000 μm, respectively, and its corresponding total thermal resistance is 8.255 K/W. According to the simulation results, the total thermal resistance of whole micro‐channel heat sink Rtotal is 7.596 K/W, which agrees well with the analysis result of thermal resistance network model.Research limitations/implicationsThe convection heat transfer coefficient is calculated approximatively here for convenience, and that may induce some errors. Originality/value –The maximum difference in temperature of the optimized micro‐channel cooling heat sink is 59.064 K, which may satisfy the requirement for removal of high heat flux in new‐generation chips.

With increased processor cores and performance for CPU/GPU, thermal design power (TDP) of these products are increasing. Traditional air-cooling solutions are sometimes insufficient to cool high density, high powered CPUs. Liquid cooling solutions can support higher power but would drive for significant initial capital investment and may not be the best solution for cooling if total cost of ownership (TCO) is high. Hence advanced air-cooling solutions like Extended Volume Air Cooling (EVAC) heat sinks are more ideal to adopt. These heat sinks use heat pipes or thermosiphon tubes to transfer the heat to regions where more physical volume is available for additional heat exchangers to deliver the best overall performance. With these extra cooling surfaces (outriggers), the thermal performance of the heat sink can be improved.The characterization of EVAC at the component level is much less straightforward than standard heat sinks due to the complexity of air flow distribution among different sections of an EVAC heat sink. This airflow distribution must be understood in order to determine effects by and on the surrounding system. This paper shows two methodologies to characterize EVAC heat sink performance at component level.The first one is to apply a thermal resistance network methodology with wind tunnel testing results of sections of the heat sink so that the cooling contribution of each section can be individually characterized for design optimization on EVAC heat sink as well as for cooling performance estimation for what-if scenario analysis in a system so that system trade-off can be investigated to optimize system trade-off to provide overall better system cooling performance. The thermal resistance network methodology described in this paper can accurately predict the EVAC heat sink thermal performance independent of system boundary conditions at different locations on the heatsink. It can also be used to optimize the overall EVAC performance. The network thermal resistance model predicts the thermal performance within 3-6% of error compared to the test results.The second methodology is to design a wind tunnel test setup with other key components (DIMM in this paper) included from a specific system so that the airflow is somewhat representative as in that system. This methodology is meant to provide a repeatable and easy-to-setup way to benchmark and compare EVAC HS performance across different designs, vendors and/or builds.This paper also shows the test results of an EVAC heat sink prototype in a spread core system to assess the cooling performance gain comparing to a non-EVAC HS. While EVAC improves CPU cooling, it could have negative impact on other system components depending on the placement of the outriggers. This paper showcased the system cooling balancing between CPU and DIMM, with different EVAC design. EVAC heatsink described in this paper can provide 20-30% improvement in thermal performance of CPU and reduces memory cooling capability by 5-15% depending on the EVAC location

We develop a method requiring minimal computations to optimize the fin thickness and spacing in a fully shrouded longitudinal-fin heat sink (LFHS) to minimize its thermal resistance under conditions of hydrodynamically and thermally developed laminar flow. Prescribed quantities are the density, viscosity, thermal conductivity and specific heat capacity of the fluid, the thermal conductivity and height of the fins, the width and length of the heat sink, and the pressure drop across it. Alternatively, the length of the heat sink may be optimized as well. The shroud of the heat sink is assumed to be adiabatic and its base isothermal. Our results are relevant to, e.g., microchannel cooling applications where base isothermality can be achieved by using a heat spreader or a vapor chamber. The present study is distinct from the previous work because it does not assume a uniform heat transfer coefficient, but fully captures the velocity and temperature fields by numerically solving the conjugate heat transfer problem in dimensionless form using an existing approach. We develop a dimensionless formulation and compute a dense tabulation of the relevant parameters that allows the thermal resistance to be calculated algebraically over a relevant range of dimensionless parameters. Hence, the optimization method does not require the time-consuming solution of the conjugate problem. Once the optimal dimensionless fin thickness and spacing are obtained, their dimensional counterparts are computed algebraically. The optimization method is illustrated in the context of direct liquid cooling.

Improved hollow cathode magnetron deposition for producing high thermal conductivity graphite-copper composite