Parametric Structure-Preserving Model Order Reduction

In sub-90 nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated parameters. Variations in the critical process parameters can result in significant fluctuations in the switching speed and leakage power consumption of different transistors in the same chip. In this paper, we study the impact of process variation on issue queues. Due to process variation, issue queues can take variable access latency. In order to work with nonuniform access latency issue queues, by exploiting ready operands of instructions at dispatch time, we propose a process variation aware issue queue design. Experimental results reveal that, for a 64-entry issue queue with half of the entries affected by process variation, our technique recovers most of the lost performance due to process variation and incurs a performance penalty of less than 2% with respect to the performance of issue queues without process variation.

A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65nm gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of response surface methodology (RSM) using design of experiments (DOE) and least squares method (LSM), are employed to generate a for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by at least 6X on a normalized basis, against worst case design

The quality of a delay test set hinges not only on test patterns and the distribution of the delay defects but on the variations in process parameters as well. Process variations result in the same delay test set displaying differences from die to die in the detection of particular delay defects at the identical circuit node. The application of an identical test set to all devices independent of process variations consequently results in delivering inefficiencies in test time utilization. This paper proposes a delay test technique that adaptively changes the size of the test set based on the position of the device in the process variation space in order to maximize test quality within a given test time.

BackgroundStochastic biochemical reaction networks are commonly modelled by the chemical master equation, and can be simulated as first order linear differential equations through a finite state projection. Due to the very high state space dimension of these equations, numerical simulations are computationally expensive. This is a particular problem for analysis tasks requiring repeated simulations for different parameter values. Such tasks are computationally expensive to the point of infeasibility with the chemical master equation.ResultsIn this article, we apply parametric model order reduction techniques in order to construct accurate low-dimensional parametric models of the chemical master equation. These surrogate models can be used in various parametric analysis task such as identifiability analysis, parameter estimation, or sensitivity analysis. As biological examples, we consider two models for gene regulation networks, a bistable switch and a network displaying stochastic oscillations.ConclusionsThe results show that the parametric model reduction yields efficient models of stochastic biochemical reaction networks, and that these models can be useful for systems biology applications involving parametric analysis problems such as parameter exploration, optimization, estimation or sensitivity analysis.

Selected results of research connected with the development of a (3D) geostatistical hydrogeochemical model of the Klodzko city area, dedicated to the spatial and time variation in the quality parameters in the Klodzko water supply system (SW part of Poland) have been presented. The research covers the period 2007-2011. Spatial analyses of the variation in three quality parameters, i.e. Fe iron (g/m 3 ) content, Mn manganese (g/m 3 ) content and NH4 + ammonium ion (g/m 3 ) content, were carried out. Spatial and time variation in the parameters was analyzed on the basis of the data (2007-2011). The input for the studies was the chemical determinations of the quality parameters of water samples taken in the Klodzko water supply system area (also treated water) in different periods of time. These data were subjected to spatial analyses using geostatistical methods. The parameters of the assumed theoretical models of directional semivariograms functions of the studied regionalized variables, were used in the ordinary (block) kriging estimation. Generally, the behaviour of the quality parameters in the Klodzko water supply system has been found to vary in space and time. Thanks to the multivariate spatial analyses some regularities in the variation in the water supply system in the Klodzko city area have been identified. In the considered time interval, the shapes of the directional Fe iron content semivariogram show a tendency to vary periodically. The courses of the directional semivariograms of Mn manganese content and NH4 + ammonium ion content show some tendencies towards directional variation over the passing years. There are visible distinct increasing trends of variability for Mn content and stronger variation are observed for NH4 + ion content. The kriging estimation results were used to determine the levels of elevated values Z* of the water quality parameters in the years 2007-2011 and to forecast these values for the years 2012-2014. The maximum values Z* of the quality parameters were stated for the years: 2007, 2008-2009 and 2012 (the decreasing trend in Fe iron content averages Z* variation towards the year 2012, the increasing trend in Mn content averages Z* variation towards the year 2012 and the increasing trend in NH4 + ion content averages Z* variation towards the years 2008-2009 and then the decreasing trend towards the year 2012).

Process variations in nanometer technologies are becoming an important issue for cutting-edge FPGAs with a multi-million gate capacity. Considering both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, we first develop closed-form models of leakage and timing variations at the FPGA chip level. Experiments show that our models are within 3% from Monte Carlo simulation, and the leakage and delay variations can be up to 3/spl times/ and 1.9/spl times/, respectively. We then derive analytical yield models considering both leakage and timing variations, and use such models to evaluate FPGA device and architecture under process variations. Compared to the architecture similar to a commercial FPGA and device setting from ITRS roadmap, device tuning alone improves leakage yield by 39% and architecture and device co-optimization increases leakage yield by 73%. We also show that LUT size 4 gives the highest leakage yield, LUT size 7 gives the highest timing yield, but LUT size 5 achieves the maximum combined leakage and timing yield. To the best of our knowledge, this is the first in-depth study on FPGA device and architecture co-evaluation considering process variations.

Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware components. This is severe in the case of memory components as minimum sized transistors are used in their design. In this work, by considering on-chip data caches, we study the effect of access latency variations on performance. We discuss performance losses due to the worst-case design, wherein the entire cache operates with the worst-case process variation delay, followed by process variation aware cache designs which work at set-level granularity. We then propose a technique called block rearrangement to minimize performance loss incurred by a process variation aware cache which works at set-level granularity. Using block rearrangement technique, we rearrange the physical locations of cache blocks such that a cache set can have its "n" blocks (assuming a n-way set-associative cache) in multiple rows instead of a single row as in the case of a cache with conventional addressing scheme. By distributing blocks of a cache set over multiple sets, we minimize the number of sets being affected by process variation. We evaluate our technique using SPEC2000 CPU benchmarks and show that our technique achieves significant performance benefits over caches with conventional addressing scheme

One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.

The inter-die and intra-die variations in process parameters (in particular, threshold voltage (Vt)) can lead to large number of failures in an SRAM array, thereby, degrading the design yield in nanometer technologies. To improve parametric yield of nano-scaled memories, different circuit and architectural level techniques can be used. In this paper, we first analyze and model different SRAM failures due to parameter variations, and discuss test methodologies to test for process variation induced failures. Next, we describe two different self-repairing techniques?at the circuit level, using adaptive body biasing and at the architecture level, using Built-in-self-test (BIST), redundancy and address remapping. The discussed self-repair mechanisms can improve design yield much beyond what can be achieved using row/column redundancy and error correcting codes (ECC) alone.

The concept of chip-to-chip information propagation by spoof surface plasmon polariton (SSPP) meta-surface at terahertz frequency has been introduced of late, that promises data transfer with high bandwidth, low crosstalk, and low energy consumption. As the exotic electromagnetic properties of the metasurface derive from its designed geometric pattern and periodicity, any possible variation of fabrication process parameters may affect the design pattern and consequently the information capacity of SSPP interconnects. In this work, we have investigated the extent of performance degradation of SSPP interconnect with the statistical variation of geometric pattern of the metasurface. We also described the technique of the design of appropriate analog circuit so that the loss of signal integrity incurred by the process variation can be recuperated in real time.

Manufacturing has been incapable of keeping up with Moore's law without significantly increasing process variability and imposing massive geometric restrictions on design. This paper highlights the design impact of variability and geometric constraints - including traditional design rules and pattern-scale constraints - and describes our approach for evaluating and enforcing pattern-scale restrictions on design.

We present an in-depth analysis of the nanowire and nanotube device performance under process variability. While every process parameter variation drastically affects the conventional MOSFET performance, we found that nanowire/nanotube FETs are significantly (> 4X) less sensitive to many process parameter variations.

In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correlations due to intra-chip variation. A lognormal distribution is used to approximate the leakage current of each gate and the total chip leakage is determined by summing up the lognormals. In this work, both subthreshold leakage and gate tunneling leakage are considered. The proposed method is shown to be effective in predicting the CDF/PDF of the total chip leakage. The average errors for mean and sigma values are -1.3% and -4.1%.

A simulator named CASTAM, which includes both process and device models, has been developed to predict MOS process variations through the analysis of variations in electrical characteristics of fabricated MOS devices using the Monte Carlo method. Analysis accuracy using the simulator is examined. Investigation shows that process parameter variations can be estimated with an error of less than 10 percent if an appropriate set of device characteristic items is chosen. Wafer inspection data for a CMOS pilot line can be analyzed with this simulator, and the main cause of threshold voltage variation pinpointed. Predictions derived from the analyzed results have been confirmed using experimental data. This shows that analysis using CASTAM is sufficiently reliable.

Thermal management of Integration Circuit (IC) becomes more and more important with the scaling of CMOS technology and dramatic increase of power density. Performance of thermal management application is highly related to the accuracy of the temperature monitoring devices. However, due to increasing process variations and parameter drifts, temperature measurements by on-chip thermal sensors may not be accurate unless these sensors are calibrated before shipping the devices to the users. Existing calibration methods impose large time cost and cannot be used for in-field calibration. In this paper, we propose a technique to calibrate on-chip thermal sensors during manufacturing as well as in-field. We model the cyclic dependence between leakage power and temperature and perform calibrations to evaluate the calibration accuracy. Experimental results on 100 dies with different process variation parameters and three corner cases show that our technique have very high accuracy.