Parasitic Conduction on Ω-Gate Nanowires SOI nMOSFETs

Mobility coupling effects due to remote Coulomb scattering (RCS) are demonstrated for the first time in FD-SOI CMOS devices subjected to front and back interface electrical degradation. The evolution with stress time of the front and back threshold voltages as well as of the low field mobility values has been obtained. The front and back interface mobility degradations were then correlated to the stress induced interfacial charge variations for each stressed interface. This enabled the clear demonstration of the existence of mobility coupling effects between the front and back interface by RCS through the silicon film.

A method of recursive images to solve transient heat diffusion in multilayer materials

Distinct frequency dependencies of the acoustic backscattering by zooplankton of different anatomical groups have been observed in our previous studies [, ICES J. Mar. Sci. 49, 97–106 (1992); Stanton et al., ICES J. Mar. Sci. 51, 505–512 (1994)]. Based mainly on the spectral information, scattering models have been proposed to describe the backscattering mechanisms of different zooplankton groups [, J. Acoust. Soc. Am. 103, 236–253 (1998b)]. In this paper, an in-depth study of pulse compression (PC) techniques is presented to characterize the temporal, spectral, and statistical signatures of the acoustic backscattering by zooplankton of different gross anatomical classes. Data collected from various sources are analyzed and the results are consistent with our acoustic models. From compressed pulse (CP) outputs for all three different zooplankton groups, two major arrivals from different parts of the animal body can be identified: a primary and a secondary arrival. (1) Shrimplike animals (Euphausiids and decapod shrimp; near broadside incidence only): the primary one is from the front interface (interface closest to the transducer) of the animal and the secondary arrival is from the back interface; (2) gas-bearing animals (Siphonophores): the primary arrival is from the gas inclusion and the secondary arrival is from the body tissue (“local acoustic center of mass”); and (3) elastic shelled animals (Gastropods): the primary one is from the front interface and the secondary arrival corresponds to the subsonic Lamb wave that circumnavigates the surface of the shell. Statistical analysis of these arrivals is used to successfully infer the size of the individual animals. In conjunction with different aspects of PC techniques explored in this paper, a concept of partial wave target strength (PWTS) is introduced to describe scattering by the different CP highlights. Furthermore, temporal gating of the CP output allows rejection of unwanted signals, improves the output signal-to-noise ratio (SNR) of the spectra of selected partial waves of interest, and provides a better understanding of the scattering mechanism of the animals. In addition, it is found that the averaged PWTS can be used to obtain a more quantitative scattering characterization for certain animals such as siphonophores.

CdTe device performance was simulated as a function of band alignment at the emitter/absorber and absorber/back buffer layer to determine under what conditions devices are front and back interface limited. When the back buffer layer forms an electron reflector, devices are limited by four separate mechanisms. When there is no electron reflector, the role of the back buffer layer increases. In addition to the front and back interfaces, Shockley-Reed-Hall (SRH) recombination can also determine the device performance. We determine the voltage at which SRH recombination dominates device performance for a number of carrier lifetimes. Finally, we show that increasing the CdTe dopant density reduces but does not eliminate the role of the back interface. These results help us interpret the improvements of real-life measurements, and will allow us to develop better front and back interfaces to CdTe.

The application of Field Effect Transistors (FETs) to sensors and biosensors allows a mass production, low cost, small size, fast response and, also, the possibility of integrating the device and conditioning signal circuit in the same integrated circuit (IC). The Ion Sensitive Field Effect Transistor (ISFET), invented in 1970 by Piet Bergveld (1), is a device similar to the conventional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), except that the metal gate is replaced by an inert electrode/pseudo electrode and a sample solution, in order to expose the gate oxide layer to ions present in the solution. The solution charges change the electrical potential in the gate oxide surface and, consequently, the device threshold voltage changes as a function of the ion concentration in the sample solution, being used as a pH sensor. Thus, the ISFET is a very promising device to Point-of-Care (POC) monitoring, such as COVID-19 control (2) and for continuous in vivo monitoring ion activity in biological processes (3)-(6).The BESOI (Back Enhanced Silicon-On-Insulator) MOSFET is a device patented in 2015 by João Antonio Martino and Ricardo Cardoso Rangel (7). This device is easy to fabricate and low cost. In the last years, the research using this device as a sensor/biosensor has been done (8)-(14). This paper presents, for the first time, the BESOI MOSFET working as an Ion Sensitive Field Effect Transistor (ISFET): the BESOI ISFET. Therefore, the focus of this work is to study the device electrical behavior influenced for pH standard solutions.The BESOI ISFET was fabricated at Integrated System Laboratory (LSI) from University of Sao Paulo (USP), Brazil. It is a planar device made on a SOI (Silicon-On-Insulator) wafer with three conventional photolithography steps, in an analogous way to previous work (15) and one more photolithography step to create microchannel and microreservoirs with SU-8 (16) layer to contain the sample solution. The wafer has no doping process (there is only the natural wafer doping of 1015 cm-3). The silicon channel layer and the gate oxide (SiO2) thicknesses are 10 nm and 25 nm, respectively. The buried oxide layer thickness is 200 nm. The drain and source contacts are fabricated with nickel and the contact pads using aluminum. The Figure 1 presents the final device layout and the Figure 2 shows the device schematic drawn.Differently from a conventional ISFET, where the drain current flows at the front interface, in the BESOI ISFET the drain current flows at the back interface. As the BESOI ISFET is a non-intentionally doped device, the free conduction charge layer is formed by biasing the Back Gate electrode (VGB). When a positive enough VGB is applied, electrons are attracted and accumulated at the back interface, and therefore, current flows from source to drain when VDS (Drain bias) is applied. A Platinum (Pt) pseudo-electrode is used to apply front-gate voltage (VGF) to the sample solution.The experimental drain current (IDS) as a function of the front-gate voltage (VGF), for 25 V applied at the back-gate (VGB), is presented in Figure 3.A, which is possible to observe that the neutral pH (pH7) curve stayed between the acid pH (pH4) curve, in the left, and alkaline pH (pH10) curve, in the right. This result shows that the threshold voltage (VTH) is lower for acid pH and higher for alkaline pH, what is compatible with the conventional ISFET results present in the literature (17). To corroborate the experimental measurement result, the device simulation was made with TCAD-Sentaurus (18), based in the paper (19). Figure 3.B shows the same trend for the simulated device with pH solution for any VGB value.In Figure 4, the threshold voltage was analyzed as a function of the pH for different VGB values. The VTH increases (becomes more positive) for alkaline pH values, regardless of the VGB applied. However, the VTH variation in the pH range, between pH4 and pH10, is different for different VGB values. With higher VGB applied, higher is the VTH variation. In Figure 5 Is possible to see clearly that the sensitivity (ΔVTH /ΔpH) increases with the VGB increase probably due to the small influence of the series resistance. In another hand, the acquired sensitivity values for VGB higher than 15 V in this work (about 25-33 mV/pH, approximately), is compatible with results present in the literature for conventional ISFETs with silicon dioxide (SiO2) for gate insulator (20). Figure 1

In this paper, the influence of interface charges (fixed charges and interface traps) on the subthreshold region was analyzed focusing on the fin height. This influence was analyzed from Triple gate SOI FinFETs (devices with a high silicon height-hfin) to Ω-Gate Nanowires (with a small hfin). The results shows that as the fin height becomes smaller, the influence of interface charges is reduced due to the better electrostatic coupling. When the fin height becomes small enough, the interface charges did not influence both subthreshold swing and threshold voltage, even for wide devices, thanks to the supercoupling.

A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given "critical" dose. Above this dose, we still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic conduction is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies.

Numerical analysis of metal-semiconductor junctions ITO/p-a-Si:H and n-c-Si/Al on silicon heterojunction solar cells

Many results have demonstrated that high interfacial recombination is one of the main leading to low power conversion efficiency (PCE) of Cu2ZnSn(S,Se)4 (CZTSSe). Herein, interfacial recombination of CZTSSe solar cell by addition of silicon nitride (SiNx) buffer layer in front interface of CdS/CZTSSe and back interface of CZTSSe/Mo is reduced. It is found that the PCE decreases sharply when the SiNx layer is deposited at the front interface. Quantitative analysis indicates that the decreased PCE is mainly attributed to the decrease in photogeneration density (JL), followed by increase in reverse saturation current density (J0). However, when the SiNx layer is deposited at the back interface, the PCE increases from 9.11 to 9.78% as the thickness of the SiNx increases from 0 to 5 nm. Quantitative analysis indicates that the increased PCE is mainly attributed to the increase in JL, followed by the decrease in J0 and series resistance (Rs). This work provides a reference for the study of using SiNx passivation to improve the efficiency of CZTSSe or other solar cells.

Performance metrics of current transport in pristine graphene nanoribbon field-effect transistors using recursive non-equilibrium Green's function approach

Solution-processed indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) have been widely researched for various applications due to their excellent electrical properties, such as high on/off current ratio, good uniformity and low processing temperature. However, intrinsic defects, such as oxygen vacancy (Vo) and weakly bonded oxygen result in instability of solution-processed IGZO TFTs. Additionally, the adsorption of oxygen and water vapor from ambient atmosphere onto the exposed channel layer is considered as major factors for the degradation of the exposed IGZO TFTs. Under positive bias stress (PBS), the adsorption of oxygen molecules on the back channel can cause the capture of electrons, resulting in enhanced carrier depletion and a positive threshold voltage shift (ΔV TH).Hafnium oxide (HfO₂), when deposited via a sol-gel process, is commonly used as a passivation layer for IGZO TFTs due to its ability to enhance device stability. The diffusion of Hafnium(IV) ions (Hf4+) into the back-channel region effectively suppresses oxygen vacancies (Vₒ), which are a major source of electrical instability. However, this suppression can lead to a reduction in carrier mobility due to reduced carrier density or scattering at the interface. Moreover, excessive diffusion of Hf4+ or residual species from the low temperature sol-gel process potentially introduce new trap states at interface, leading to a degradation of both carrier mobility and subthreshold swing (SS).This study aims to improve the stability of IGZO TFTs while maintaining electrical performance using an organic-inorganic passivation layer. The passivation layer consists of a poly(methyl methacrylate) (PMMA)/HfO₂ double-stacked structure, both deposited via spin-coating, with thicknesses of approximately 145 and 7 nm, respectively. The PMMA layer serves as a buffer layer, offering smooth and pinhole-free coverage, while preventing the direct contact between inorganic layer and IGZO surface. The upper HfO₂ layer, derived from a sol-gel process, serves as a dense inorganic barrier on the PMMA film. It further enhances the overall barrier properties by providing a high-density protective film. Moreover, the double-stacked structure of the passivation layer extends the effective diffusion path of oxygen and improves barrier performance compared to single layer.Under a PBS test for 1000 s, ΔV TH of IGZO TFTs without passivation, with a PMMA single layer and with PMMA/HfO2 passivation were 8.4, 3.7, and 1.0 V, respectively, as shown in Fig. 1. Consequently, IGZO TFTs with organic-inorganic passivation layer, fabricated employing mild spin-coating processes, demonstrated greater stability under PBS tests. Additionally, IGZO TFTs with PMMA/HfO₂ passivation exhibited no significant degradation in electrical performance, maintaining a field-effect mobility of 1.25 cm²/V, as shown in Table 1.To evaluate the interface quality and investigate the charge trapping phenomenon, hysteresis characteristics were investigated, by applying gate voltage sweeps in the forward and reverse directions. As shown in Fig. 2, the hysteresis width was 0.65 (no passivation), 0.30 (PMMA), and 0.18 V (PMMA/HfO₂), respectively. Additionally, SS values for the IGZO TFTs without passivation, with a PMMA single layer and with PMMA/HfO2 passivation were 0.220, 0.206, and 0.182 V/dec, respectively, as summarized in Table 1. This progressive decrease in SS demonstrates that the PMMA/HfO2 structure improves the interface quality. Notably, the SS values before and after PBS test remained nearly unchanged for each individual device, indicating that the bias stress did not induce additional interface defects. The ΔV TH under PBS test decreased significantly from 8.4 (no passivation) to 3.7 (PMMA) and further to 1.0 V (PMMA/HfO₂), indicating that ambient-induced charge trapping is the dominant cause of instability, rather than defect formation, which can result in increased SS value. The double-stacked structure effectively suppresses the adsorption of ambient species to provide superior barrier properties compared to the single-layer PMMA passivation, thereby enhancing the bias stress stability with maintaining the electrical characteristics. Figure 1

Uniformity consideration in integrated-circuit manufacturing is an impressive task, especially in the field of nano-node semiconductors. The use of high-dielectric-constant (high-K) materials to promote drive current in deep nano-node devices is also increasing. One solution involves enhancing the quality of the high-K dielectric layer as a gate dielectric with nitridation treatment. This study combines the aforementioned concerns in deep nano-node manufacturing and demonstrates their relationship. Given the electrical measurement of the wafers treated with decoupled plasma nitridation (DPN), a few desired key parameters, including drive current (IDS), threshold voltage (Vth), gate oxide capacitance per area (Cox), subthreshold swing (SS), and interface state density, in the design of p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) are observed. A uniformity comparison with different DPN processes is also performed, and the uniformity of the gate dielectric in input/output and core zones is discussed. Based on the uniformity distribution, lower SS values are obtained by adopting the low-temperature nitridation treatment after high-K dielectric deposition. The increased nitrogen concentration decreases the deviation, thereby indicating improved uniformity of SS values.

The electrical characteristics of the fully depleted SOI transistor depend to a great extent on the properties and mode of operation of the back interface. The threshold voltage of the surface MOS device can change significantly as the back interface is driven from accumulation to depletion. Elimination of the kink effect, enhancement of the inversion-layer mobility, and an improved subthreshold slope all require that the back interface be held in depletion. Shifts in MOS transistor behavior after irradiation are typically observed in threshold voltages, subthreshold slopes, transconductances, and leakage currents associated with fixed charge accumulation and fast interface state generation at silicon-oxide interfaces. The presence of an additional exposed back interface in thin, fully depleted SOI transistors suggests that charge and interface-state variations caused by radiation-induced damage at the back interface will cause additional changes in device behavior. Hence, shifts in the behavior of fully depleted SOI transistors may be greater than in those made in thick SOI films where the top surface is shielded by the neutral region of the transistor body from changes in the back interface charge. >

We present in this paper a basic compact model incorporating several key physical mechanisms in nanowire tunneling field-effect transistors (NW-tFETs), such as non-constant subthreshold swing (SS), definition of an on voltage, ballistic transport for carriers in the channel, and quantum capacitance limit (QCL). Using experimental data from [1], the validity of this model is verified. Further, to project the performance of ultra-scaled silicon NW-tFETs, we compare the state-of-the-art gate-all-around (GAA) NW MOSFETs [2] with modeling results for the same NW diameter and EOT (effective oxide thickness). It is concluded that ultra-scaled NW-tFETs can achieve high performance with low subthreshold swing (SS) and nearly the same on current as in MOSFETs. © 2013 IEEE.

This paper presents a systematic assessment of surface roughness limited mobility in ultra-thin GeOI pMOSFET, considering wave function penetration and non-linear dependence of scattering matrix element on surface fluctuation, for the first time. The effects of body thickness, BOX material, Si capping layer, front and back interface roughness, and uniaxial strain on hole mobility are systematically investigated and understood from view point of scattering matrix element. This paper shows that, in order to enhance hole mobility, GeO2 as buried oxide is better than SiO2. Moreover, Si capping, decrease of roughness at front and back interfaces, uniaxial strain are all effective. In particular, the uniaxial strain, combined with Si capping layer, shows huge potential. This paper is helpful in providing useful guidelines for mobility enhancement.