Particle Swarm Optimization based vector reordering for low power testing

This paper presented the analysis of total power dissipation of AP-DCD algorithm using field programmable gate arrays (FPGAs). The static and dynamic power dissipation investigated using leakage current, supply voltage, effective capacitance and toggling frequency of the AP-DCD algorithm. It was found that the effective capacitance of AP-DCD algorithm was the main factor for the dynamic power dissipation and leakage current was the main factor for the static power dissipation. The total power dissipation was calculated by the addition of static and dynamic power. From the simulated calculation we found that the consumption of the dynamic power (2.1 mW) was significantly less than the static power (219.75 mW) dissipation and the total power consumption was 221.85 mW. Xilinx-Virtex-II Pro XC2VP30 device is one of the commonly used programmable fabrics, which was employed here for all the calculation.

In this paper, we present a methodology for systematically optimizing the power-supply voltage for either maximizing the performance of very large scale integration (VLSI) circuits or minimizing the power dissipation in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purpose, we develop simplified empirical equations that describe the transistor behavior as a function of power supply and temperature. We use these models to calculate the full-chip power dissipation as a function of power supply and temperature. We then solve the power and chip thermal equations simultaneously to calculate the chip temperature and power dissipation at a given power supply. By varying the power-supply voltage, we determine the optimum V/sub DD/ value that minimized delay per unit length in global interconnects and therefore maximizes performance. Using the same framework, by again varying the supply we find the optimum V/sub DD/ that minimized the total power dissipation while maintaining a given delay per unit length. We show that for 90- and 65-nm technologies, where leakage power represents a significant fraction of the total power dissipation, optimum V/sub DD/ for maximum performance is lower than the International Technology Roadmap for Semiconductors (ITRS) specified supply voltage. This is due to the fact that reducing V/sub DD/ results in a large reduction in total power dissipation, and therefore the chip temperature, which improves performance. This improvement in performance is greater than the performance penalty incurred due to reduction in V/sub DD/. We also show that as the required delay per unit length is increased, total chip power consumption is reduced significantly if the power supply is also reduced as compared to the case when power supply is fixed at the nominal value. This change becomes larger with technology scaling due to the fact that leakage power, which is a very strong function of chip temperature, becomes a larger fraction of the full-chip power dissipation.

Total power dissipation in RSFQ circuits consists of two parts, dynamic and static. Dynamic power is dissipated in Josephson junctions performing useful logical and data transmission operations. This dissipation is fundamental and proportional to the data rate (at 4 K, of the order of 10/sup -18/ Joule per bit). Static power is dissipated in resistors used by RSFQ circuits to distribute dc bias current between Josephson junctions. This part of dissipation is not intrinsic to RSFQ circuits and in principle can be eliminated. The goal of this work is to show that Delay Insensitive (DI) RSFQ primitives can be modified so that resistors are no longer required in the dc power supply distribution network, so that the on-chip static power dissipation is absent. In this report we present the schematics for such primitives, define the class of circuits that allow resistor-free current distribution network, and formulate the requirements to the design of this network.

Leakage current consumes the majority of the active mode energy in the high-performance integrated circuits of today. In particular, in high microprocessor and system-on-chip architectures, the SRAM cell array is the primary source of leakage current. So low-leakage SRAM design is essential. Today’s VLSI designs are all about cutting down on power dissipation, supply voltage, leakage currents, and chip area. However, raising these parameters increases sub-threshold leakage currents and power dissipation, reducing design performance. Increasing the cell area reduces leakage power dissipation in standby mode. To solve these problems, it is best to cut down on effective leakage currents and dynamic power dissipation. For low voltage and energy constraints, the power dissipation, area, and delay performance of the low-power design of the 6T-SRAM cell with the DTMOS technique for a proposed low-power SRAM will be implemented in the Tanner EDA tool in 22 nm technology. The power of both types of SRAM cells will be compared using low-power techniques and a power analysis.

This conference paper presents the design and implementation of a low-power 4-bit Arithmetic Logic Unit (ALU) with a Random-Access-Memory (RAM) module on Cadence platform. The proposed ALU architecture aims to address the growing demand for energy-efficient processors in modern computing systems. In this work, we leverage advanced low-power design techniques to optimize the ALU's static leakage power by around 66.24% while ensuring minimal performance degradation. The design uses minimum required transistors with power gating to reduce dynamic and static power dissipation. Power Gating is performed by shutting down the power for a portion of the design in order to reduce the static(leakage) power in the design. Furthermore, we introduce an integrated RAM module within the ALU architecture to enhance overall data handling capabilities and minimize data access latency. The RAM is carefully designed to consume minimal power during read and write operations, contributing to the overall energy efficiency of the ALU. The proposed design is simulated and validated on the Cadence platform to assess its performance and power characteristics. The simulation results demonstrate significant improvements in power efficiency compared to conventional ALUs without compromising on critical performance metrics. Moreover, the integrated RAM module showcases notable gains in data handling and access speed. In conclusion, the presented low-power 4-bit ALU design with an integrated RAM module on Cadence offers a promising solution for energy-conscious computing systems.

Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We introduce a new buffer design approach with selective use of high threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.

The performance prospects for 4H-SiC Bipolar Junction Transistors (BJTs) and Insulated Gate Bipolar Transistors (IGBTs) are theoretically evaluated. The total power dissipated (Ptotal) for both devices is calculated as a function of lifetime in the drift region and blocking voltage and used as a figure of merit to compare and contrast the effectiveness of different semiconductor materials for bipolar device applications. Assuming a maximum of 300W/cm2 for the total permissible power dissipation due to heat sink constraints we estimate an upper limit of 5kV for SiC BJT operation.

In sub-70 nm technologies, leakage power becomes a significant component of the total power. Designers address this concern by extensive use of adaptive voltage scaling techniques to reduce dynamic as well as leakage power. Low-power scan test schemes that have evolved in the past primarily address dynamic power reduction, and are less effective in reducing the total power. We propose a power-managed scan (PMScan) scheme which exploits the presence of adaptive voltage scaling logic to reduce test power. We also discuss some practical implementation challenges that arise when the proposed scheme is employed on industrial designs. Experimental results on benchmark circuits and industrial designs show a significant reduction in dynamic and leakage power. The proposed method can also be used as a vehicle to trade-off test application time with test power by suitably adjusting the scan shift frequency and scan-mode power supplies.

Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scaling has been used to reduce both dynamic and leakage power in caches. However, aggressive voltage reduction causes process-variation--induced failures in cache SRAM arrays, which compromise cache reliability. In this article, we propose FFT-Cache, a flexible fault-tolerant cache that uses a flexible defect map to configure its architecture to achieve significant reduction in energy consumption through aggressive voltage scaling while maintaining high error reliability. FFT-Cache uses a portion of faulty cache blocks as redundancy—using block-level or line-level replication within or between sets—to tolerate other faulty caches lines and blocks. Our configuration algorithm categorizes the cache lines based on degree of conflict between their blocks to reduce the granularity of redundancy replacement. FFT-Cache thereby sacrifices a minimal number of cache lines to avoid impacting performance while tolerating the maximum amount of defects. Our experimental results on a processor executing SPEC2K benchmarks demonstrate that the operational voltage of both L1/L2 caches can be reduced down to 375 mV, which achieves up to 80% reduction in the dynamic power and up to 48% reduction in the leakage power. This comes with only a small performance loss (<%5) and 13% area overhead.

As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is dissipated in the cache hierarchy. To reduce cache leakage, individual cache lines can be kept in drowsy mode, a low voltage, low leakage state. Every cache access may then result in dynamic power consumption and performance penalties. A trade-off between the amount of leakage power saved on one hand, and the impact on dynamic power and performance on the other hand must be reachedTo affect this trade-off, we introduce caches in which the power level of cache lines is controlled with the cache replacement policy. In a slumberous cache, cache lines are maintained at different power save modes which we call levels, which depend on their order of replacement priorities.We evaluate the trade-offs in the context of PLRU, a common cache replacement algorithm. We explore various assignments of the tranquility levels to lines and compare overall power and performance impacts. As technology scales down, the dynamic power required to energize slumberous cache lines drops drastically while the leakage power savings remain roughly steady. The performance penalty--in cycles-- remains constant with technology scaling for each scheme we evaluate.

As on-chip cache size has increased considerably in recent high-performance microprocessor technologies, power dissipation and leakage current in SRAM have become critical. High-performance IC designs use multi-port cache memory to provide the needed accessibility and bandwidth. Since the word and bit lines cover the foot-print of the entire cache section, duplicating the word and bit lines for multiple ports results in large silicon area and increases bitline discharge and power dissipation. As technology scales down device size and supply voltages, static power dissipation has emerged as a critical factor in total system power dissipation. In this paper, we present an area-and energy-efficient multi-port cache memory architecture, which employs isolation nodes, local sense amplifiers and dynamic memory partitioning techniques, to facilitate simultaneous multi-port accesses without duplicating bitlines. The proposed cache memory architecture also reduces bitline latency.

A large amount of leakage power could be saved by increasing the number of idle virtual channels (VCs) in a network-on-chip (NoC). Low-leakage power switch is proposed to allow saving in power dissipation of the NoC. The proposed NoC switch employs power supply gating to reduce the power dissipation. Two power reduction techniques are exploited to design the proposed switch. Adaptive virtual channel technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating (PG) reduces the average leakage power consumption of proposed switch. The proposed techniques save up to 97% of the switch leakage power. In addition, the dynamic power is reduced by 40%. The traffic-based virtual channel activation (TVA) algorithm is used to determine the traffic status and send adaptation signals to PG units to activate/deactivate the VCs. The TVA algorithm optimally utilizes VCs by deactivating idle VCs to guarantee high-leakage power saving with high throughput. TVA is an efficient and flexible algorithm that defines a set of parameters to be used to achieve minimum degradation in NoC throughput with maximum reduction in leakage power. The whole network average leakage power has been reduced by up to 80% for 2-D-mesh NoC with throughput degradation within only 1%. For 2-D-torus NoC, a saving in power of up to 84% is achieved with <2% degradation in throughput. The implementation overhead of TVA is negligible.

The greatest challenge in VLSI design is reduction of power dissipation. Due to the scaling, the leakage current of sub- threshold plays a key role in the total dissipation of power. This paper illustrates the application of reduction in power dissipation using Self-Controllable Voltage Level (SVL) Technique for a half adder using FinFETs 32nm technology. The circuit supplies a higher dc voltage to the required active-load circuit and in standby mode decreases the dc voltage given to the load circuit. Half Adder consumes low power and low leakage when compared to conservative design with SVL technique. The total power dissipation can be reduced by applying the upper Self Controllable voltage level technology that uses increased supply potential and Lower Self Controllable voltage level technology that uses raised ground potential. This paper represents how to manage power by means of SVL techniques. Based on power consumption and propagation delay the Half Adder using SVL technique is highly preferable as compared to conventional design. Low power method is anticipated to reduce power in nanoscale CMOS-VLSI systems using SVL technique. The results illustrate that there is noteworthy reduction in power incorporation of Half Adder in allusion mode. This design is greatly helpful in designing the systems that consume low power. The circuit is designed using Hspice and EDA Tools in 32nm Technology.

Motion estimation is the power-hungry block in the video compression system. The sum of absolute difference (SAD) is the most repeated operation in block matching algorithms of the motion estimation subsystem. This paper identifies low-power full adder that is used in the proposed SAD architecture. The proposed SAD method consumes low power as compared to the existing SAD architectures. The designs are implemented using ASIC flow (synthesis) using the Cadence tools and the simulations are done using the Modelsim simulation tools. The synthesis is done using TSMC 180 nm and 45 nm technology libraries; the synthesis is mainly focused on the power consumed, area acquired and latency. This paper implements 4 × 4 (16 input samples) SAD algorithm, and the proposed architecture shows 26.3 % improvement in leakage power, 67.58 % improvement in dynamic power, and 65.6 % improvement in the total power with the 180 nm technology and 13.9 % improvement in the leakage power, 62 % improvement in the dynamic power, and overall 60 % improvement of total power with the 45 nm technology, as compared to the existing architecture.

In this article, novel leakage control techniques are adopted in Feed-Through Logic (FTL) for low power high-speed designs. The FTL design has a unique feature; the outputs are partially evaluated before its input data arrive and quick final evaluation is performed as soon as input signals reach. However, FTL designs suffer from high leakage and standby current in static and dynamic modes which increase the total power dissipation. To resolve this issue leakage control techniques such as Leakage Control Transistor (LCT) and Self-Biasing Transistor (SBT) are adopted. It acts as a smart switch by virtual power gating, which reduces the voltage swing, causing the significant reduction in static and dynamic power dissipation. In addition to that mixed-mode ripple carry adder approach has been introduced using projected and basic designs. Simulation has been executed through PTM 45 nm technology using the T-spice simulator. The parametric analyses are performed to examine the reliability of the circuit through the capacitive load, supply voltage variations and the immunity to thermal noise demonstrating the effectiveness of the proposed technique. Simulation results have demonstrated that the proposed approaches achieve low power-delay product.