Partitioned-Exponent Blinding: A Countermeasure against Power Analysis Attacks

Cryptographic systems can potentially suffer from various attacks which are a consequence of vulnearability of side channel information to analysis attacks. The nature of digital circuits is prone to electromagnetic and power analysis (EMA and PA) attacks. Interconnects in cryptographic circuits emanate information through electromagnetic signals which can be exploited using EMA. Complementary Metal Oxide Semiconductor (CMOS) circuits are vulnearable to leak of computational information through leakage and dynamic power consumption. Dynamic power consumption of cryptographic engines is a rich source to sink in the data under process. The hardware implementation of cryptographic algorithms undermine the security of encrypted system against non brute-force-attacks. The attackers collect and analyse the leakage information of cryptographic circuits to detect the secrete key. The parameters sensitivity of the device and circuits make the cryptographic engines vulnearable to fault injection and inherent inconsistency of the circuits. Dynamic and static power comprise two major components of power consumption of digital circuits. Both power components vary with data under process. This exhibits power consumption has data dependency in digital circuits. To make noisy power profile, various countermeasures have been proposed against Differential Power Analysis (DPA) attacks. In this research, false glitch cells is proposed to work as a countermeasure to generate random transitions and power spikes to scramble power profile. The mathematical foundation of security implications of false glitch cells against Correlation Power Analysis (CPA) attacks is investigated. Moreoever, the security efficiency of utilizing false glitch cells is verified with different metrics.

Aimed at improving the resistance against power analysis attacks, a systematic and architectural design approach for multicore processors is proposed in this article and is demonstrated in an eight-core prototype platform with low performance overhead and hardware cost. In order to introduce randomness in both the time dimension and the amplitude dimension and make realignment extremely difficult, the proposed multicore platform leverages several methods together, such as random task scheduling (RTS), random insertion of operations (RIO), and frequency and phase randomization (FPR). Moreover, a power state monitoring and control (PSMC) scheme is proposed to defend against power analysis attacks by keeping enough background noises. A test chip of the proposed multicore processor is fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS LP technology and can operate at up to 800 MHz with a 1.2-V supply. The Advanced Encryption Standard (AES) algorithm with these randomization methods is implemented on the processor. Measurement results show that the correlation power analysis (CPA) attacks and the power analysis attacks based on convolutional neural networks (CNNs) are unsuccessful even with 2 000 000 power traces when all the countermeasures are used.

Fully depleted silicon-on-insulator (FD-SOI) technology is renowned for its back-gate bias voltage controllability. It allows devices fabricated with FD-SOI technology to be optimized for low power consumption or high performance with proper back-gate biases, depending on the required application. This article proposes using the back-gate biasing technique in novel countermeasures against power analysis attacks. Theoretical explanations are discussed, and realistic differential power analysis (DPA) attacks, targeting AES-128 encryption on a 65-nm STOB 32-bit RISC-V microcontroller, are conducted to justify the proposed idea. The experimental results show that when compared with applying no bias, applying our first proposal, which involves using forward back-gate bias, not only improves the test device performance but also enhances its resistance to DPA attacks. Moreover, vulnerability to DPA attacks is kept unchanged when a reverse back-gate bias is applied to achieve low power consumption. The DPA resistance is even more vital when combining the back-gate bias technique with a lower supply voltage. The number of power traces required to retrieve the secret key successfully increases by 14.5 times in the best case. Even better DPA resistance can be obtained when the back-gate bias of the targeted microcontroller is dynamically randomized, as suggested by our second proposal of a random dynamic back-gate bias (RDBB). When RDBB is applied, the number of power traces required to retrieve the secret key successfully significantly increases by 33.4 times.

Exchange of private information over a public medium must incorporate a method for data protection against unauthorized access. To enhance the data security against the DPA attack in network communication, a dual field ECC processor supporting all finite field operations is proposed. The ECC processor performs hardware designs in terms of functionality, scalability, performance and power consumption. A unified scheme is introduced to accelerate EC arithmetic functions. The hardware is optimized by a very compact Galois field arithmetic unit with fully pipelined technique. A key-blinded technique is designed against power analysis attacks.

Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level

Emerging technologies such as Spin-transfer torque magnetic random-access memory (STT-MRAM) are considered potential candidates for implementing low-power, high density storage systems. The vulnerability of such nonvolatile memory (NVM) based cryptosystems to standard side-channel attacks must be thoroughly assessed before deploying them in practice. In this paper, we outline a generic Correlation Power Analysis (CPA) attack strategy against STT-MRAM based cryptographic designs using a new power model. In our proposed attack methodology, an adversary exploits the power consumption patterns during the write operation of an STT-MRAM based cryptographic implementation to successfully retrieve the secret key. In order to validate our proposed attack technique, we mounted a CPA attack on MICKEY-128 2.0 stream cipher design consisting of STT-MRAM cells with Magnetic Tunnel Junctions (MTJs) as storage elements. The results of the experiments show that the STT-MRAM based implementation of the cipher circuit is susceptible to standard differential power analysis attack strategy provided a suitable hypothetical power model (such as the one proposed in this paper) is selected. In addition, we also investigated the effectiveness of state-of-the-art side-channel attack countermeasures for MRAMs and found that our proposed scheme is able to break such protected implementations as well.

Cryptographic System-on-Chips (SoCs) are becoming more and more popular. In these systems, cryptographic accelerators are integrated with processor cores to provide users with the software’s flexibility and hardware’s high performance. First, this work aimed to confirm the vulnerability of cryptographic SoCs against several types of power analysis attacks. Then, the novel Random Dynamic Frequency Scaling (RDFS) countermeasure is proposed to improve the resistance of such systems. The proposed RDFS countermeasure improved the power analysis resistance while maintaining low-performance overhead and hardware costs by generating more than 219,000 distinct frequencies for driving only the cryptographic accelerators. The effectiveness of the proposed RDFS countermeasure is demonstrated by conducting realistic Correlation Power Analysis (CPA) attacks, Deep-Learning-based Side-Channel Analysis (DL-SCA) attacks, and Test Vector Leakage Assessment (TVLA) testing methodology. The experimental results show that the RISC-V SoC protected by RDFS countermeasure can withstand CPA attacks and TVLA test with more than five million power traces, which is the best result compared to other related works. The proposed RDFS countermeasure also harden the targeted RISC-V SoC’s resistance against DL-SCA attacks.

In modern society, cryptographic algorithms that guarantee the integrity of data have been used in various fields while being secured through various research. However, since the encryption algorithms are mostly used in the computer environment, there is a difference in the amount of leakage current depending on all calculation results. A power analysis attack is a method that utilizes a difference in leakage current and is effective in attack of a cryptographic algorithm. Therefore, we propose the structure of AES encryption algorithm to cope with power analysis attack by randomizing input using scrambler so that attacker cannot input arbitrary initial value and secret key.

Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks

Power analysis attacks pose a significant threat to the security of cryptographic devices as they can reveal a secret key. Performing cryptographic operations based on a randomly varying clock (RVC) is a practical countermeasure against such attacks. The countermeasure makes it difficult to align power traces, which is a prerequisite for power analysis attacks to succeed. This paper introduces a synchronous real-time sampling (SRTS) technique as an advanced hardware-implemented approach to collect traces for a power analysis attack that negates countermeasures involving practical RVCs. By recovering the RVC, the leakage signal corresponding to the recovered clock edge is synchronously sampled in real time. We propose an analog-based hardware system implemented with two circuit blocks for SRTS operations, namely, a clock recovery block and an analog signal-processing block. The target of the power analysis attack is an Advanced Encryption Standard (AES)-128 software-implemented smart card operated at 20 MHz, which is varied in the range of 30% by the RVC countermeasure. The traces captured by the SRTS show that the suboperations of the AES encryption are distinct in contrast to the indistinguishable waveforms captured at a fixed sample rate. The results of the power analysis attack demonstrate that the correct key is successfully extracted with a high correlation coefficient at the S-box output of the AES. The proposed SRTS method improves the relative distinguishing margin by 191.4% and reduces the required number of traces to 2.75% compared with the conventional correlation power analysis attack with a fixed sample clock.

With the increasing popularity of Internet of Things Edge (IoTe) devices, RISC-V emerges as the most suitable architecture for various applications. Since attackers have direct physical access to these IoTe devices, securing these RISC-V designs is of major concern. This research article first focuses on designing a low-power high-performance, RISC-V crypto-core for high security applications, which significantly enhances the efficiency of the AES encryption algorithm, but still susceptible to Power Analysis Attacks (PAA). A novel Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure (NCVCFB) providing variation in both amplitude and temporal domains of signal was introduced to enhance AES security in RISC-V based IoTe devices, specially to address the vulnerability against PAA. The NCVCFB countermeasure employs the rolling architecture and will operate in tandem with each round of AES to obscure power consumption patterns. It will execute additional random number of rounds cyclically in the first and last round of AES, based on the randomly generated number. The newly designed, secured RISC-V achieved remarkably low area and power overheads of 1.05% and 1.23%, respectively, without affecting the maximum operating frequency. Nevertheless, the throughput was decreased due to variable clock count for different plaintext. The PAA was performed using the power traces captured from post-layout design on ASIC platform at UMC 65 nm technology node as well as on the experimental hardware setup employing a Side-channel Attack Security Evaluation Board (SASEBO). The resilience of the secured RISC-V architecture against PAA was tested by subjecting it to 2 Million traces, and none of the bytes got recovered. Thus, the NCVCFB secured RISC-V attained a Measurement To Disclose (MTD) >2M, Signal to Noise Ratio (SNR) <0.5, Mutual Information (MI) in the milli range, and Test Vector Leakage Assessment (TVLA) within +/−4.5 limits.

Wireless sensor networks (WSNs) are largely deployed in different sectors and applications, and Elliptic Curve Cryptography (ECC) is proven to be the most feasible PKC for WSN security. ECC is believed to provide same level of security such as RSA with a much shorter key length, and thus they seem to be ideal for applications with small resources such a sensor network, smartcard, RFID, etc. However, like any other cryptographic primitive, ECC implementations are vulnerable to Power Analysis Attacks (PAAs) that may reveal the secret keys by exploiting leaked power consumption from running cryptographic devices (e.g. smart cards, mobile phones etc.). In this paper, we present a comprehensive study of major PAAs and its countermeasures on ECC cryptosystems. In addition, this paper describes critical concerns to be considered in designing PAAs on ECC particular for WSNs, and illustrates the need to conduct, in the near future, intensive researches for the development of these specific PAAs.

Power analysis attacks are types of side channel attacks that are based on analyzing the power consumption of the cryptographic devices. Correlation power analysis is a powerful and efficient cryptanalytic technique. It exploits the linear relation between the predicted power consumption and the real power consumption of cryptographic devices in order to recover the correct key. The predicted power consumption is determined by using the appropriate consumption model. Until now, only a few models have been proposed and used. In this paper, we describe the process to conduct the CPA attack against AES on SASEBO-GII board. We present a comparison between the Hamming Distance model and the Switching Distance model, in terms of number of power traces needed to recover the correct key using these models. The global successful rate achieves 100% at 11100 power traces. The power traces needed to recover the correct key have been decreased by 12.6% using a CPA attack with Switching Distance model.

Power analysis attacks have emerged as a significant threat to the security of elliptic curve cryptography (ECC), necessitating the development of countermeasures that can safeguard against such attacks without compromising computational efficiency. This paper introduces an innovative approach that integrates signed factorial expansions (SFE) with random masking techniques for scalar multiplication, a critical operation in ECC. The proposed method encodes large scalar values into smaller integers and incorporates randomization to resist a variety of power analysis attacks effectively. By conducting simulations, we demonstrate that the algorithm not only maintains high computational efficiency but also exhibits excellent performance in resource-constrained cryptographic chips, which are typically vulnerable to such attacks. The algorithm's resilience is attributed to the randomization of scalar multiplication operations, which obscures the correlation between operation and power consumption, thereby thwarting attempts at key recovery by an attacker. Our simulation results validate the algorithm's ability to defend against simple power analysis (SPA), differential power analysis (DPA), zero-value register-based power analysis (RPA), zero-value point-based power analysis (ZPA), and double attack (DA) methods. This work not only enhances the security of ECC implementations but also provides a practical solution for cryptographic systems with limited resources, offering a promising direction for future research and applications in the field of cryptography.

With the advancement of IoT edge devices, the threat to sensitive data processed at these devices is increasing. This research aims to enhance processor’s built-in resilience against power analysis attacks (PAA) by expanding pipeline stages, employing diverse pipeline techniques, and integrating additional features. The paper proposes 32-bit RISC-V core micro-architectures with inbuilt cryptographic capabilities, extending the RISC-V ISA with custom AES instructions to reduce energy consumption, code size, and encryption time compared to software AES solutions. An area-efficient 128-bit, 12-clock AES based on the Masoleh S-box is integrated into the RISC-V core, resulting in low area and power overheads. Two cores are presented: Core1, a 3-stage pipelined core with a software pause, and Core2, a 4-stage pipelined core with a hardware pause for securing data with AES instructions. Despite their vulnerabilities, the integration of AES with RISC-V architecture significantly improves their intrinsic resilience against PAA. This work analyses the vulnerability and improvement in intrinsic resilience of these cores to side-channel attacks, the impact of hardware versus software pause and the effect of pipeline stages on security metrics. The proposed designs are validated on a Xilinx Basys3 FPGA and developed in UMC 65 nm technology node. Power traces generated during AES encryption are extracted using Synopsys PrimeTime PX and analyzed with a MATLAB power attack model to successfully recover all key bytes. Core1 and Core2 achieved higher throughput of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.02\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.83\times $ </tex-math></inline-formula>, respectively, than the Arm CryptoCell312. Core2’s added circuits for hardware pause and increased number of pipeline stages significantly boost performance and enhance security against power attacks, with only a modest increase in area and power consumption.