Path delay ATPG for standard scan design

In this work we propose a novel concept called state tuple to represent the states of lines in a circuit for the generation of two pattern tests. The proposed approach is described in detail for generating robust two pattern tests for path delay faults in standard scan designs. Using the proposed approach we also report experimental results of a test generator for robust path delay faults in standard scan designs. The results show that the test generator achieves high efficiency with reduced implementation complexity.

Specific physical defects of high performance circuits manifest themselves as path delay faults (PDFs). A pair (v1, v2) of test patterns is required to detect a PDF. A PDF is robust testable if there is a test pair on which the fault manifestation does not depend on delays of other circuit paths. A PDF is non robust testable if manifestation of the fault on any test pair is possible only when all other paths of the circuit are fault free. For high quality delay testing it is desirable to detect delay of any path regardless of delays of other paths. In this paper, synthesis of a circuit by covering each nonterminal node of the reduced ordered binary decision diagram (ROBDD) or free binary decision diagram (Free BDD) system with the original subcircuit from gates is suggested. Delay testability of such circuits is investigated. It is specified that the PDF of each path of the circuit is detected without injecting additional inputs into the circuit. It is well known that the BDD is a directed acyclic graph based on the Shannon decomposition in each nonterminal node v: 0 1 i i x x v i v i v f x f x f = = = ∨ . Here fv is the function corresponding to the node v, and the decomposition variable xi marks the node v. The dashed edge drops in the node corresponding to the function 0 i x v f = , and the bold edge drops in the node corresponding to the function 1 i x v f = . The BDD is called ordered (OBDD) if variables are encountered in the same order in all paths connecting the BDD root with the terminal node. The BDD is called reduced (RBDD) if it does not contain either isomorphic subgraphs or nonterminal nodes such that 0 1 i i x x v v f f = = = . An example of reduced and ordered BDD (ROBDD) is shown in Fig. 1. When deriving the Free BDD, a suitable decomposition variable is chosen for each nonterminal node v independently of other nonterminal nodes. That may cut the number of Free BDD of nonterminal nodes in comparison with the ROBDD (for the same function). Let 1 { ,..., } m F f f = be a system of Boolean functions describing combinational circuit behavior. Derive the ROBDD using the same order of variables for each Boolean function from F. Join isomorphic subgraphs in different ROBDDs. Combine different ROBDDs of 1-terminal nodes into one 1-terminal node and their 0-terminal nodes into one 0-terminal node. As a result, we obtain the graph with m roots and two terminal nodes. This graph represents a system of m Boolean functions. It is called the shared ROBDD. Without loss of generality, we will further consider systems with one function as an example. In Fig. 1, the ROBDD for one Boolean function is shown. The ROBDD represents the disjoint sum of products (DSoP) of the function f as follows:

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. In addition, it can potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of handling large numbers of paths. A parameter called Δ is used to control the number of funtional faults targeted and thus the number of tests generated. If Δ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. An appropriate subset of tests can be selected once the implentation is known. The test sets generated for various values of Δ are fault simulated on gate-level realizations to demonstrate their effectiveness. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.

Scan design has been widely used for alleviating the burden of test generation. How to reduce the extra costs caused by the scan design becomes a major target now. Previous approaches have tried individually to enhance the abilities of test generation algorithm and scan cell selection strategy. In contrast, a global strategy taking care of the close relationship between these factors and combining a new scan structure is proposed in this paper. Reducing the test application time which may dominate the cost testing a mass product is the goal of this research. First of all, a new scan structure named gradually-on (GO) structure which allows for the scan cells in the scan chain to be gradually turned on is used. Two assertions for the design of test generator are proposed next, and a fault list oriented test generation algorithm is developed in accordance with these two assertions. A simulation based partial scan methodology is finally introduced for selecting the suitable scanning flip-flops one by one through the means of sufficiently utilising the dynamic information generated during fault simulation. Experimental results show that overall consideration of scan design and test generation is able to speed up test generation and reduce a great amount of test application time

To reduce total chip production costs, circuits must be more testable. Several design for testability schemes which tradeoff various design parameters have been proposed toward that end. The recently proposed partial reset (PR) method is incorporated. Rather than allowing all memory elements in a sequential circuit to be reset by a primary input, only a subset of them is given the capability to reset. PR has less hardware overhead and typically smaller test application times than scan design, PR, furthermore, allows unrestricted at-speed testing. The tradeoff is in slightly lower testability. A dynamic PR flip flop selection method is described utilizing a fast sequential test generator. The automated system developed in this research works closely with the test generator to insert PR, observability enhancements and partial scan into a given circuit. The result is higher fault coverage than is possible with PR alone and faster test application times than scan design. Results are shown on all ISCAS'89 circuits, up to s9234. Even though multiple runs of test generation is performed, CPU times are comparable to a single run of conventional deterministic automatic test pattern generations.

We describe a procedure based on an existing static timing analysis tool for selecting path delay faults to target during test generation. The use of an existing static timing analysis tool ensures that a state-of-the-art process can be used for estimating path delays. However, static timing analysis, by itself, can be inaccurate as it does not take into consideration conditions that are necessary for detecting path delay faults. In the proposed method, these conditions are captured as what are called input necessary assignments, which static timing analysis tools are able to use. By providing the static timing analysis process with the input necessary assignments for a selected path, the static timing analysis process can estimate the delay of the path more accurately. It can also identify additional paths whose delays are at least as high as those of the selected paths. Thus, feeding back the input necessary assignments to the static timing analysis process enhances the correlation between static timing analysis and actual timing of tests on silicon. The result is a set of potentially detectable path delay faults associated with critical paths based on more accurate estimates of the path delays that can be exhibited by a test set, compared with the set that would be obtained by static timing analysis alone.

The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has typically applied a worst case voltage drop at all points along a circuit path which leads to a very conservative analysis. We also show that in certain cases, the traditional analysis can be optimistic, since it ignores the possibility of voltage shifts between driver and receiver gates. In this paper, we propose a new analysis approach for computing the maximum path delay under power supply fluctuations. Our analysis is based on the use of superposition, both spatially across different circuit blocks, and temporally in time. We first present an accurate model of path delay variations under supply drops, considering both the effect of local supply reduction at individual gates and voltage shifts between driver/receiver pairs. We then formulate the path delay maximization problem as a constrained linear optimization problem, considering the effect of both IR drop and LdI/dt drops. We show how correlations between currents of different circuit blocks can be incorporated in this formulation using linear constraints. The proposed methods were implemented and tested on benchmark circuits, including an industrial power supply grid and we demonstrate a significant improvement in the worst-case path delay increase.

The problem of test generation for path delay faults in synchronous sequential circuits is addressed. In existing testing methods, a single fast clock cycle is used to activate path delay faults and a fault is said to be detected only if the fault free response is different from the faulty response at a single output and at a specified time unit in the test sequence. We refer to these methods as single fast clock cycle and single observation time testing methods. We show that testable faults may exist, which are untestable using a single fast clock cycle and a single observation time. Such faults are testable when multiple fast clock cycles and/or multiple observation times are used. A test generation procedure is given that uses multiple fast clock cycles and multiple observation times. Experimental results are presented on MCNC synthesis benchmarks to demonstrate the effectiveness of the proposed strategy in increasing the fault coverage and reducing the test length.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A complete system which takes the test generation algorithm, the scan cell selection strategy and the structure of the scan chain into account is proposed. It is totally different from the traditional approaches which try to enhance the ability of the individual subject. The goal of this research is to reduce the extra costs caused by the scan design, especially the test application time. Experimental results show that the overall consideration of scan design and test generation can speed up test generation and greatly reduce the amount of test application time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An approach to generate test pattern for the path delay fault model using a modified stuck-at TPG tool which has been used for industrial purposes for years is presented. We discuss constraints derived by the definition of non-robust delay tests and show that, under some circumstances, the requirements accepted in literature are not sufficient to derive non-robust tests due to possible test invalidation, even in the absence of any additional faulty delay. Finally, we discuss possible constraints which have influence on the test quality and show that test generation for robust tests can not be tackled if a stuck-at TPG tool is used without any delay fault simulation.

An approach to the design of multilevel, multi-output combinational logic circuits in which all path delay faults are detectable by robust tests is proposed. Inadequacies of previous approaches for synthesis for testability of path delay faults are discussed. A necessary and sufficient condition for the existence of a hazard-free robust test for a path is stated. Violation of this condition is adopted as the criterion for identifying the paths, in a given circuit, which are not testable by hazard-free robust tests. Transformation methods to render these paths testable are proposed. >

Existing delay test generation techniques focus on test generation for combinational blocks, and assume the inputs and outputs of the block to be unconstrained. Test application for delay tests is done by means of enhanced scan, scan shifting or functional justification; all these techniques impose minimal constraints on the inputs and the outputs of the combinational block targeted. This leads to over-testing the components for delay defects. This paper analyzes the gains associated with determining the multi-cycle (sequential) sensitization of delay tests. The advantages of determining multi-cycle sensitization is then illustrated on benchmark designs with and without a delay-specific fault model.

Current test generation algorithms for path delay faults assume a variable-clock methodology for test application. Two-vector test sequences assume that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such tests may be acceptable for combinational circuits, their use for nonscan sequential circuit testing is impractical. A rated-clock path delay simulator shows a large drop in coverage for vectors obtained from existing test generators that assume a variable clock. A new test generation algorithm provides valid tests for uniform rated-clock test application. In this algorithm, signals are represented for three-vector sequences. The test generation procedure activates a target path from input to output using the three-vector algebra. For an effective backward justification, we derive an optimal 41-valued algebra. This is the first time, rated-clock tests for large circuits are obtained. Results for ISCAS-89 benchmarks show that rated-clock tests cover some longest, or close to longest, paths.

Full scan designs are widely used for their indisputable benefits of predictably high test coverage, diagnosis and debug. However, for high-performance designs the cost of scan - area and delay - is not acceptable and partial scan is used instead. Unfortunately, partial scan significantly increases test generation complexity. We define a structured partial scan design methodology and specific test generation enhancements, which significantly enhance test coverage and reduce test data and cycles. Selective design areas use special types of nonscan cells which can capture a value in the last few scan load cycles. Combinational test generation is extended to work with this structured partial scan design, resulting in higher coverage and fewer patterns. Experimental results on industrial designs show consistent testability benefits.

Path delay fault model is the most suitable model for detecting distributed manufacturing defects which can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability of many practical designs is very low. In this paper we show how to resynthesize a combinational circuit in order to reduce the total number of paths in the circuit. Our results show that it is possible to obtain circuits with a significant reduction in the number of paths while not increasing area and/or delay of the longest sensitizable path in the circuit. Research on path delay testing shows that in many circuits a large portion of paths does not have a test that can guarantee detection of a delay fault. The path delay testability of a circuit would increase if the number of such paths is reduced. We show that addition of a small number of test points into the circuit can help reducing the number of such paths in the given design.