PDN impedance modeling of 3D system-in-package

In this paper, we show the advantages of 3-D stacked through silicon via (TSV) in high chip density package in aspect of wideband and low power distribution network (PDN) impedance. We selected large size (80 μm) and large pitch (200 μm) TSV with thick silicon substrate (Si, 80 μm, aspect ratio =1) for on-chip PDN, and compared two total PDN impedances of a PDN with TSVs and a PDN with wire-bondings depending on number of stacked chips from 2 to 10 on a single package. PDN impedance with TSVs includes total capacitance and inductance of TSV and 20 mm × 20 mm package substrate. PDN impedance with wire-bondings shows total capacitance and inductance of wire-bondings and same size package substrate. PDN impedance with TSVs has lower levels with wide bandwidth from 10 MHz to 5 GHz except serial resonance frequency range of the package substrate around 350 MHz. In low frequency range from 10 MHz to 350 MHz, total capacitance of a PDN with TSVs is larger than that of a PDN with wire-bonding because of 0.1 μm thickness silicon oxide (Si02) for blocking DC leakage from TSV to Si substrate. Over 350 MHz, total inductance of a PDN with TSVs is smaller than that of a PDN with wire-bonding because TSV is the smallest electrical path from top surface of stacked chips to the package PDN. The effectiveness of lowering total PDN impedance is better when the number of stacked chips is growing because total length of TSVs is linearly increased with factor 1 while total length of wire-bonding is done with factor √2.

A semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can be integrated on HBM interposer which enables a terabyte/s bandwidth system. On the HBM interposer, significant numbers of I/O are integrated and they tend to operate at the same time which leads to severe simultaneous switching noise (SSN). When SSN occurs, the performance of system can be heavily degraded. Total SSN is strongly related to the self-noise and transfer-noise. In this point of view, a proper PDN design to manage transfer noise which is closely related to transfer-impedance must be taken into account. The analysis of power distribution network (PDN) impedance of HBM interposer must be performed since it generally affects power supply to the chips as well as signal integrity (SI). In this paper, HBM interposer with five layers is designed to analyze PDN. For PDN impedance analysis, Z-parameters depending on the various physical dimensions are simulated and compared. PDN impedance of HBM interposer is simulated and analyzed in the interest of frequency range dominated by interposer PDN. In order to suppress SSN, we suggest a metal-insulator-metal (MIM) de-cap scheme which can be commonly available for HBM interposer to reduce PDN impedance. Based on the designed physical dimension and material properties of HBM interposer, we successfully shows the suppression of SSN.

In this paper, the imperativeness of low power distribution network (PDN) impedance on printed circuit board (PCB) with high frequency signals operating at hundreds of Mega-Hz range and the impact of embedded capacitance material (ECM) in minimizing wideband PDN impedance are discussed. The study to compare the performance of PCB with ECM versus conventional dielectric FR4 material was conducted with post-layout power integrity simulation using Keysight ADS on the power net of interest, followed by measurement of PDN impedance and simultaneous switching noise (SSN) using network analyzer (VNA) and oscilloscope respectively on prototype PCB. Lastly, eye diagram and jitter of the high frequency clock signal on the PCB are observed. The correlated simulation and measurement results are presented and discussed in the later section of this paper.

Power integrity design has been becoming important in the advanced CMOS digital systems, because power supply noise induces logic instability and electromagnetic radiation. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation, and result in large electromagnetic radiation. In this paper, effects of damping condition of the total PDN impedance on power supply noise have been studied by adding variable on-die RC circuit to the intrinsic on-die RC circuit in chip PDN. Two types of test chips were designed with different variable on-die PDN impedances. By varying the values of on-die RC circuit, the simulated waveforms of power supply noises for the two test chips have been changed from oscillatory region to damped regions.

A 2.5D/3D multi die interposer with TSV (Through Silicon Via) allows massive wide parallel busses between memory and logics devices, improves speed, and significantly reduces power consumption. The TSV and silicon interposer are amongst the most promising technologies that offer the greatest vertical interconnects density. This new establishment will change the semiconductor industry paradigm for many years to come. 2.5D/3D technology introduces a new degree of electrical design complexity which is unfamiliar to many existing electrical design methodologies and EDA tools. A new electrical verification methodology must be developed with consideration to the micro level (TSV and interposer structures) and macro/system level simulation. At the Micro level, modeling of TSV is challenging due to its dependency on the material properties of the medium surrounding it and its impact on the signal losses/attenuation, capacitance effects, and the coupling among the vertical interconnects. At the Macro level, new electrical characteristics of the system need to be closely coupled with the thermal and mechanical tolerances of the entire 2.5D/3D packaging structure in order for its ultra wideband data exchange between logic chip and memory chips. TSV placement on logic and memory chips must be carefully placed during the chip design placement stage in order to avoid unnecessary electromagnetic coupling and faulty logic latching. Traditional separate signal and power integrity analysis methodologies are no longer sufficient due to the close proximity of the power and signal distribution network. In order to accurately predict the performance of 2.5D/3D packages, a new design paradigm shift is needed to toggle 2.5D/3D system performance optimization. New design and modeling approaches along with new breeds of computational electromagnetic EDA tools, are paramount to predicting the performance of 2.5D/3D packages.

Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-\mu \mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-\mu \mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $\mu$ -bumps with $25-\mu \mathrm{m}$ size on a $45-\mu \mathrm{m}$ pitch in the logic and $25-\mu \mathrm{m}$ size on a $55-\mu \mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-\mu \mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to integrate multiple functionalities and cost.

In this paper, we propose a deep reinforcement learning (DRL)-based power distribution network (PDN) structure design optimization method for high-bandwidth memory (HBM) interposer. Due to the usage of multi-voltage PDNs and various components in limited PDN space, the design optimization of interposer PDN is required. The proposed method provides an optimal PDN shape and area that can satisfy target impedance. For the verification of the proposed method, the initial PDN and optimized PDN using the proposed method are compared in terms of PDN impedance and PDN shape. We successfully optimize the PDN shape and area while satisfyings target impedance. By applying the proposed method to test interposer PDN, about 23% of the area was saved for design constraint such as the expansion of other PDNs and placement of various components.

In this paper, we design and analyze the hierarchical power distribution network (PDN) for full wafer scale chip (FWSC) module. With its high bandwidth and low latency, FWSC has been considered a promising solution in the artificial intelligence (AI) processor market. However, the huge size of FWSC inevitably leads to long current paths and high impedance that consequently cause large IR drop and power/ground noise. In an effort to overcome these issues, the hierarchical PDN of FWSC module is designed in a 3D structure that allows direct interconnection from PCB to chip to minimize the current path. Although there are several studies related to PDN design for FWSC module, they conducted limited analysis on a specific PDN only. We design the hierarchical PDN for FWSC module composed of PCB PDN, multi-array silicone rubber socket (SRS)-based PDN, multi-array through wafer via (TWV)-based PDN, and on-chip PDN. Each PDN component was modeled into equivalent circuit models. Then, we fully analyzed the overall hierarchical PDN impedance in the frequency domain.

This paper focuses on the modeling and analysis of different power distribution network (PDN) structures in 3D TSV ICs, including 3D full wave model and equivalent circuit model. In addition, a simplified equivalent circuit model of stacked PDN is proposed to analysis aspects influencing stacked PDN impedance, such as number of ground TSVs, number of TSV pairs and number of stacked layers. Analyses about how these aspects influencing total capacitance, inductance of stacked PDN and causing resonance in PDN self-impedance (Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) are made in detail. What's more, power noise in different stacked PDN structures is calculated and analyzed in time domain to evaluate their power integrity features. Analysis in this paper can offer instructions for the design and analysis of on-chip PDN.

Comparisons between organic and ceramic packaging is a difficult task given the considerable number of differences in material properties and potential tradeoffs between cost, electrical performance, thermal performance, and environmental factors. This paper presents a power and signal integrity comparison between a select set of multilayer organic technologies (HDBU and CPCore) and multilayer ceramic technologies (HTCC and LTCC). The geometry and material property impact on electrical performance for the flip-chip first level interconnect are qualitatively discussed and compared. The broadband frequency performance for the ball grid array (BGA) second-level interconnect to a PWB is simulated and characterized to 40 GHz for a differential pair using full-wave simulation. The impedance of the power distribution network (PDN) for a ceramic package is characterized by measurement to correlate with full-wave simulation to then subsequently compare with an organic substrate PDN.

In this paper, we analyzed a power distribution network (PDN) impedance considering thermal distribution. Due to the development of integrated circuits (ICs) towards high density and high performance, the supply voltage has been reduced while power density has been increased. Shrunk supply voltage causes a low voltage margin and high temperature caused by the high power density varies the circuit parameters of the PDN. Thus, considering the operating temperature effects for a robust PDN design is essential. However, the previous power integrity analysis is not focused on temperature effects on PDN. Hence, impedance analysis of PDN considering thermal distribution is essential. Therefore, this research analyzed thermal distribution effects on the self-impedance of PDN. By using a W-element model, we analyzed thermal distribution effects on PDN self-impedance by circuit simulation. As a result, the difference in self-impedances is observed between the PDNs with other thermal distributions in spite of current loop path and mean temperature; The capacitance has same value as the capacitance considering mean temperature of thermal distribution; The value of the resistance closes to the resistance considering the temperature at the probing point, not the mean temperature.

This paper reports a novel wet chemical etching method, referred to as uniform metal-assisted chemical etching (MaCE), for uniform hole formation in fabrication of through silicon vias (TSVs) on silicon (Si) interposer in wafer level. In MaCE, a layer of Au as catalyst is deposited on the photolithography-patterned Si surface. Uniform holes are formed by simply immersing the Au-loaded Si into a hydrofluoric acid-hydrogen peroxide aqueous solution. In a typical experiment, ~1 million holes are formed after MaCE for 4 h at room temperature over a 4-in Si wafer with a diameter of 28 μm, a depth of 162 μm, a pitch size of 80 μm, and a sidewall roughness below 50 nm. The holes show high geometric uniformity in wafer level, with their depth in the range 159-164 μm, the diameter in 27.1-29.7 μm, and high verticality. Simultaneous etching of two wafers in the same batch is also demonstrated. The TSV etched by MaCE show compatibility with SiO2 deposition by plasma-enhanced chemical vapor deposition and copper filling by electroplating. The reported method provides an approach for manufacturing TSV on Si interposer with simple operation, high geometric uniformity, high throughput, and low cost.

As the complexity of a modern microprocessor increases rapidly, the methods of testing/debug take up increasing silicon area and create a cumbersome routing problem. The core power distribution network (PDN) of a microprocessor supplies power to a majority of underlying circuits. In this paper, we propose to explore use of the PDN in a microprocessor as a communication channel for test/debug purposes. Although, there are some common characteristics with power line communications (PLC) over power grid in a residential network, PLC over a PDN is very different in channel characteristics, tolerance to voltage fluctuations and noise characteristics. Further, decoupling capacitors attached to the package and the PDN of a microprocessor makes the PDN a bulky low pass filter. However, it is well known that the parasitic inductance of a decoupling capacitor is more significant beyond the self resonant frequency, and our measurements on an Intel microprocessor indicates that the low pass filter becomes leaky at higher frequencies beyond 1 GHz. In this work, measurements are used to model the PDN of a microprocessor as a communication channel and estimate the path loss characteristics as well as the channel impulse response. Link budget is calculated for the proposed communication system and receiver design considerations are derived. Measurement results and power supply noise analysis indicate that the use of jitter-robust pulse shapes, spread-spectrum techniques and strong coding would be required to communicate reliably over the PDN of a microprocessor.

We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D and 3-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surface-mounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the ultralow impedance evaluation system that has a high measurement dynamic range at the entire measurable frequency band can be realized. Furthermore, by using 2.5-D and 3-D FEM electromagnetic field simulator, it is expected that the accurate and wideband comparative verification of the PDN impedance analysis and evaluation can be realized.

Many applications for future generations of logic and memory chips will be requiring highly sophisticated computing functions at low cost. Small form factors, portability, and low cost will require low power operation. While continued scaling of silicon technology to dimensions below quarter micron devices and interconnections appears technically feasible, higher levels of integration and operation at higher speed have been driving the power consumption of logic chips up instead of down. This paper discusses how scaled submicron silicon technology can provide leverage to reduce power, while gaining in throughput for logic chips, and in capacity for memory functions. Strong reductions in voltage supply have to accompany shrinking dimensions. Materials limits such as tunneling currents through ultra-thin silicon-dioxide gate dielectrics and electromigration in minimum pitch interconnections emerge to be key challenges to realize low power 0.1 /spl mu/m level CMOS circuits. A more than 10/spl times/ gain in productivity as measured by the energy*delay product can be realized by shrinking from 0.5-0.125 /spl mu/m CMOS device technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>