Performance Analysis of FFT Algorithms on Multiprocessor Systems

Chapter 6 - Fast Fourier transform methods

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

Discrete Fourier transform (DFT) has many applications in digital signal and image processing and other scientific and technological domains, but its time complexity of direct computation is O(n2), limiting greatly its application range. Thus many people have developed fast Fourier transform (FFT) algorithms, reducing the complexity from O(n2) to O(nlogn)(In this paper logn denotes log2n).But for large n, O(nlogn) is still very high. So multiprocessor systems have been used to speed up the computation of DFT. This paper first introduces a new general method to deduce FFT algorithms, then transforms the deduced second radix-2 decimation-in-time FFT algorithm into another parallelizable sequential form, and finally transforms the latter algorithm into a new parallel FFT algorithm, reducing the time complexity of DFT to O(nlogn/p) (where p is the number of processors). Using similar methods, the authors can also design other new parallel 1-D and 2-D FFT algorithms.

Recent research presents a technique to enumerate all valid assignments of “twiddle factors” for power-of-two fast Fourier transform (FFT) flow graphs. Brute-force search employing state-of-the-art Boolean satisfiability (SAT) solvers can then be used to find FFT algorithms within this large solution space which have desirable characteristics. Surprisingly, this approach has discovered FFT algorithms requiring fewer operations than the split-radix algorithm even when all twiddle factors are nth roots of unity. This paper reviews and then extends this prior research to examine fast discrete convolution algorithms when implemented via FFT and inverse FFT (IFFT) algorithms. In particular, we find that the combination of FFT and IFFT algorithms in fast convolution permits greater freedom when selecting valid twiddle factor assignments. We exploit this freedom and use SAT solvers to find new fast convolution algorithms with the lowest operation counts known.

This paper presents a scaled radix-2/8 fast Fourier transform (FFT) (SR28FFT) algorithm for computing length- N = 2m discrete Fourier transforms (DFTs) scaled by complex number rotating factors. The idea of the SR28FFT algorithm is from the modified split radix FFT (MSRFFT) algorithm, and its purpose is to furnish other algorithms with high efficiency but without shortcomings of the MSRFFT algorithm. A novel radix-2/4 FFT (NR24FFT) algorithm and a novel radix-2/8 FFT (NR28FFT) algorithm are proposed. These two algorithms use SR28FFT to calculate their sub-DFTs of odd-indexed terms. Several aspects of the two algorithms such as computational complexity, computation accuracy, and coefficient evaluations or accesses to the lookup table all are improved. The bit-reverse method can be used for their order permutation and no extra memory is required to store their extra coefficients by the two novel algorithms, which contribute significantly to the performance of the FFT algorithms. The SR28FFT algorithm can also be applied to other algorithms whose decomposition contains sub-DFTs of powers-of-two. The Appendix presents an algorithm named SR28FFT-2 for further reducing the number of arithmetic operations, and NR24FFT and NR28FFT algorithms based on SR28FFT-2 requires fewer real operations than that required by the MSRFFT algorithm.

In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT. These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on Field-Programmable Gate Arrays (FPGAs) for all proposed algorithms. We also discuss the design criteria of the twiddle factor multiplication. Finally it is shown that there is a trade-off between twiddle factor memory complexity and switching activity in the introduced algorithms.

In this paper, we propose a low multiplier and multiplication complexities 256-point fast Fourier transform (FFT) architecture, especially for WiMAX 802.16a systems. Based on the radix-16 FFT algorithm, the proposed FFT architecture utilizes cascaded simplified radix-24 single-path delay feedback (SDF) structures. The control circuit of the proposed simplified radix-24 SDF FFT architecture is simple. The hardware requirement of the proposed FFT architecture only needs 1 complex multiplier and 56 complex adders for supporting 256-point computations. The computation complexity of multiplications and the hardware complexity of the proposed FFT architecture need less complexity than both complexities of the previous FFT structures in 256-point FFT applications. In hardware verifications, the output throughput rate of our FFT design processes up to 35.5M samples/sec with Xilinx Virtex2 1500 FPGA, and it processes up to 51.5M samples/sec with UIMC 0.18?m standard cell technology. The throughput rate of this implementation is suitable for WiMLAX 802.16a application, whose maximum sample rate is 32MHz.

To reduce or eliminate the interprocessor communications, I. Gertner, R. Tolimieri, and their colleagues proposed an M-D fast Fourier transform (FFT) algorithm, called the reduced transform algorithm (RTA). In the present work, the idea of RTA is extended to the M-D Cooley-Tukey (C-T) FFT algorithm and M-D Good-Thomas (G-T) prime factor algorithm. A new implementation strategy for these algorithms that requires no interprocessor communication is discussed. A hybrid algorithm which combines the C-T or G-T algorithm with RTA is also described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In recent past, we developed 4×8 and 4×16 processing element (PE) template-based Coarse-Grain Reconfigurable Arrays (CGRAs) and mapped different length and type of Fast Fourier Transform (FFT) algorithms on them. In this paper, we have considered radix-4 and radix-(2, 4) FFT accelerators which were generated from 4 × 8 and 4 × 16 PE CGRA templates respectively. We estimated their power and energy consumption while radix-4 accelerator was processing 64 and 1024 points and radix-(2, 4) accelerator was processing 64 and 128 points of FFT algorithms. The power consumption was estimated by timing simulation of postfit gate-level netlist of both of the accelerators for a Field Programmable Gate Array (FPGA) used as target platform. Based on the measurements, we have compared both of the accelerators for their power and energy consumption.

The split-radix approach for computing the discrete Fourier transform (DFT) is extended for the vector-radix fast Fourier transform (FFT) to two and higher dimensions. It is obtained by further splitting the (N/2*N/2) transforms with twiddle factors in the radix (2*2) FFT algorithm. The generalization of this split vector-radix FFT algorithm to higher radices and higher dimensions is also presented. By introducing a general approach for constructing the fast Hartley transform (FHT) from the corresponding FFT, new vector- and split-vector-radix FHT algorithms with the same desirable properties as their FFT counterparts are obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Signal processing plays an important role in the field of communication Engineering.The amount of data that is received is processed by using different algorithms.Discrete Fourier Transform (DFT) is one of the technique that is used to compute the data.Direct computation of DFT results in complexity; as a result Fast Fourier Transform (FFT) is one of the algorithms to reduce the complexity.The proposed paper presents the parallel-pipelined implementation of radix-2 fixed point 32-point FFT algorithm using state machine as controller and fixed point pipelined implementation of Linear CORDIC that operates for the angles- .The result of 64-point FFT are obtained in M= clock cycles due to multi processor technique.Initially FFT functionality is checked using MATLAB and finally simulated and synthesized using Xilinx ISE 14.1.Besides CORDIC algorithm is implemented in both MATLAB and in Xilinx on Virtex-7.The main objective of this work is to obtain an area efficient FFT and CORDIC without performance loss that could be used as a part of Signal processing.

This work presents simulation, analysis and experimental verification of Fast Fourier Transform (FFT) algorithm for shunt active power filter based on three-level inverter. Different types of filters can be used for elimination of harmonics in the power system. In this work, FFT algorithm for reference current generation is discussed. FFT control algorithm is verified using PSIM simulation results with DLL block and C-code. Simulation results are compared with experimental results for FFT algorithm using DSP TMS320F28335 for shunt active power filter application.

Objectives: For Orthogonal Frequency Division Multiplexing (OFDM), Fast Fourier Transform (FFT) processoris required. So, in this work, a variable point Pipelined FFT processor is designed by utilizing Verilog language. Further transmitter and receiver blocks are designed to form OFDM system. Methods: Speed enhancement is the key area which is been looked into this project work. Pipelined Architecture that is going to be implemented is RS2DF (Radix-2 Single path Delay Feedback). Standard FPGA Flow is adapted to implement this project i.e., right from specification to bit file generation. Simulations and Synthesis will be done using Questasim and Xilinx ISE. Verilog Simulations will be compared with in-built MATLAB FFT Core. MATLAB is used for reference and verification. Findings: This Project clarified the usage of FFT IP and OFDM in Xilinx ISE focusing on a specific family of FPGA. The execution of the proposed algorithm ought to perform superior to anything the base algorithm with the all-out basic way getting additionally advanced along these lines expanding the speed of activity. maximum operation frequency achieved was 236.189MHz but in base paper maximum operation frequency was 30Mhz. The systems utilized are Interna1 and externa1 Pipe1ining of modules and Distributed LUT based idea, the target of the above methods is to lessen the basic way deferral and increment the general speed of activity of structure, the disadvantage is the increments in area and output latency. Area is not of a much issue as present day days FPGAs has immense measure of assets. Output 1atency should be taken consideration with additional rationale at whatever point FFT is coordinated with other system modules. Application: The project depicts technique for streamlining timing basic ways of FFT to work at higher-speeds, to be utilized as a feature of LTE Protoca1 or any wire1ess protoco1 such as WLAN and LDACS. Keywords: Fast Fourier Transform (FFT), Hardware Description Language (HDL), Orthogonal Frequency Division Multiplexing (OFDM), Pipeline, Verilog

Fixed-point arithmetic is used to provide faster and smaller implementations in many digital signal processing applications, including medical imaging, at the expense of decreased accuracy. In particular, when a Fast Fourier Transform (FFT)-Inverse Fast Fourier Transform (IFFT) pair are required as part of the calculation, the error introduced into the calculations can be significant. For some applications, such as Fourier Domain Optical Coherence Tomography (FD-OCT), this degradation is unacceptable. Our study shows that using a conventional fixed-point FFT-IFFT pair, such as Xilinx's FFT core, can produce an average 6-bit error for a 1024-point FFT using 12-bit input data in a 32-bit arithmetic system. The majority of the error is caused by quantization effects, particularly on the phase information of input signal. For this reason, in phase sensitive applications such as FD-OCT, the error dominates the fixed-point calculation: 78% in 16-bit and 51% in 32-bit systems. This work presents a parameterized 32 to 4096-point integer FFT implementation for FPGAs that uses a Split-Radix algorithm to reduce the number of multiplies and improve latency. Integer FFTs are perfectly reconstructible, with zero reconstruction error. Here, we specifically analyze a 1024-point Integer Split-Radix FFT (Int-SRFFT) and IFFT pair that perfectly reconstructs the original 12-bit input data using 22-bit arithmetic, compared to the average 6-bit error for a 1024-point FFT using 32-bit fixed-point arithmetic. The pipelined architecture of this design has a latency of 29.06us for a 1024-point FFT, and a throughput of more than 34 thousand 1024-point FFTs/second for a 22-bit datapath at an operating frequency of 274MHz. Although our Int-SRFFT is perfectly reconstructible, compared to Xilinx's fixed-point FFT, it has ~6% more flipflops, ~63% more LUTs, 5.3x more BRAMs, and a ~44% increase in latency. However, compared to a previous fixed-point SRFFT design on an FPGA, our throughput is 15.5x greater.

FFT(Fast Fourier Transform) 알고리즘에는 DIT(Decimation-In-Time)와 DIF(Decimation-In-Frequency)가 있다. DIF 알고리즘은 Radix-2/4/8 등의 다양한 종류와 그 구현 방법이 개발되어 사용되고 잇으나, DIT 알고리즘은 순차적인 출력을 낼 수 있는 장점이 있음에도 불구하고 다양한 알고리즘이 연구되지 못하였다. 이 논문에서는 새로운 DIT Radix-4 FFT의 나비연산기(butterfly) 구조를 제안하고 검증하였다. 제안 구조를 사용하여 64-point FFT 구조를 설계하고 Verilog로 코딩하여 구현함으로써 제안 구조의 효용성을 입증하였다. 48개의 곱셈기를 사용하여 합성하였으며 678만 게이트 수를 나타내었다. 따라서 제안된 DIT Radix-4 FFT 구조는 순차적인 FFT 출력을 필요로 하는 OFDM 통신용 SoC(System on a Chip)에 사용될 수 있을 것이다. Two basic FFT(Fast Fourier Transform) algorithms are the DIT(Decimation-In-Time) and the DIF (Decimation-In-Frequency). In spite of the advantage of the DIT algorithm is to generate a sequential output, various structures have not been made. In this paper, a new DIT Radix-4 FFT butterfly structure are proposed and implemented using Verilog coding. Through synthesis, it is shown that the 64-point FFT is implemented by 6.78 million gates. Since the proposed FFT structure has the advantage of a sequential output, it can be used in OFDM communication SoC(System on a Chip) which need a high speed FFT output.