Performance analysis of synchronous multibuffered packet-switching networks

Because of their ability of nonblocking and fault tolerance, multistage-multipath networks provide useful characteristics for ATM switches and large-scale parallel computers. In this paper an analytical model for the analysis of ATM switches based on multistage-multipath packet switching interconnection networks with finite buffering capacity at the output of switching elements is presented. The proposed model is general in that it analyzes ATM switches under uniform and nonuniform traffic. First, a general model of synchronous buffered switching element, using output buffering, under an assumption of finite buffer size for a very general class of traffic patterns, is presented. It is assumed that the subsequent stages of the network are nearly independent, and a model is extended for the entire network under this assumption. The analytical results obtained with the proposed model are then compared with the results obtained for single path networks, and it is shown that the model is general enough for the class of multipath networks.

Interconnection networks usually consist of a fabric of interconnected routers, which receive packets arriving at their input ports and forward them to appropriate output ports. Unfortunately, network packets moving through these routers are often delayed due to conflicting demand for resources, such as output ports or buffer space. Hence, routers typically employ arbiters that resolve conflicting resource demands to maximize the number of matches between packets waiting at input ports and free output ports. Efficient design and implementation of the algorithm running on these arbiters is critical to maximize network performance.This paper proposes a new arbitration algorithm called SPAA (Simple Pipelined Arbitration Algorithm), which is implemented in the Alpha 21364 processor's on-chip router pipeline. Simulation results show that SPAA significantly outperforms two earlier well-known arbitration algorithms: PIM (Parallel Iterative Matching) and WFA (Wave-Front Arbiter) implemented in the SGI Spider switch. SPAA outperforms PIM and WFA because SPAA exhibits matching capabilities similar to PIM and WFA under realistic conditions when many output ports are busy, incurs fewer clock cycles to perform the arbitration, and can be pipelined effectively. Additionally, we propose a new prioritization policy called the Rotary Rule, which prevents the network's adverse performance degradation from saturation at high network loads by prioritizing packets already in the network over new packets generated by caches or memory.

Interconnection networks usually consist of a fabric of interconnected routers, which receive packets arriving at their input ports and forward them to appropriate output ports. Unfortunately, network packets moving through these routers are often delayed due to conflicting demand for resources, such as output ports or buffer space. Hence, routers typically employ arbiters that resolve conflicting resource demands to maximize the number of matches between packets waiting at input ports and free output ports. Efficient design and implementation of the algorithm running on these arbiters is critical to maximize network performance.This paper proposes a new arbitration algorithm called SPAA (Simple Pipelined Arbitration Algorithm), which is implemented in the Alpha 21364 processor's on-chip router pipeline. Simulation results show that SPAA significantly outperforms two earlier well-known arbitration algorithms: PIM (Parallel Iterative Matching) and WFA (Wave-Front Arbiter) implemented in the SGI Spider switch. SPAA outperforms PIM and WFA because SPAA exhibits matching capabilities similar to PIM and WFA under realistic conditions when many output ports are busy, incurs fewer clock cycles to perform the arbitration, and can be pipelined effectively. Additionally, we propose a new prioritization policy called the Rotary Rule, which prevents the network's adverse performance degradation from saturation at high network loads by prioritizing packets already in the network over new packets generated by caches or memory.

This paper presents a model that can be easily used to resolve the energy hub operation problem. The proposed model considers the uncertainty in the input and output ports. The energy hub optimum operation problem needs to be resolved in order to supply several energy loads in combination at the minimum total energy cost. In this study, mixed-integer linear programming was applied to formulate this optimization problem. The power balance, energy storage, and converter limitations of the input and output ports were included as equality and inequality constraints. The total cost of an energy hub was determined by the price of energy carriers. Eventually, deterministic and stochastic versions of the proposed model were tested in a case study. In the test system, electricity, gas, and wind generation were used in the input port, and the output port contained the electrical and thermal load. The results demonstrated that a stochastic model based on different scenarios was more realistic than a deterministic model. However, the total operating cost of an energy hub decreased more in the stochastic model compared to the deterministic model.

A formulation for design of continuous, hinge-free compliant mechanisms is developed and examined within a continuum structural topology optimization framework. The formulation makes use of two distinctly different sets of springs, the first of which are artificial springs of relatively large stiffness attached to the input and output ports of the mechanism model, and the second of which are springs attached only to the output port with smaller stiffnesses that represent the resistance of the workpiece as it is manipulated by the mechanism. The proposed formulation involves solving two nested optimization problems. In the inner problem the arrangement of a constrained amount of structural material is optimized to maximize the mechanism's mutual potential energy in response to a force loading at the input port while working against the stiff artificial springs on the input and output ports. As the relative stiffness of the artificial springs increases, the material continuity of the mechanism also increases to the point where de facto ‘hinge’ regions are eliminated. In the outer problem, the artificial springs are removed and one solves for an appropriate amount of structural material that yields the desired finite deformation compliance characteristics of the mechanism when working against the real workpiece resistance. Different aspects of the proposed formulation are demonstrated on a number of examples and discussed. Copyright © 2004 John Wiley & Sons, Ltd.

In this paper, we purpose a novel approach to analyze exact cell loss probability of Shared Buffer ATM switch. In a N X N ATM switch whose input ports and output ports share one buffer, the number of arriving cells from input ports at one time slot is less than or equal to N. If these cells were destined to n output ports, no cells will be destined to the remaining N-n output ports. In the extremism, all arriving cells were destined to one output port, no cell will be destined to the other N-1 output ports. So, the arriving cells at each time slot from the input ports are destined to the output ports correlatively, but not independently. For this reason, the analyzing result on the assumption that all output cell queues are independent one another is larger than actual result. We complete our analysis by three steps. First, considering the case that there are cells arriving from input ports but not cells remove from output ports, we can get one-step state transition probability matrix P<SUB>a</SUB>; Second, considering the case that there are cells removing from output ports but not cells arrive from input ports, we can get one-step state transition probability matrix Ps; Third, considering arrival process and service process are independent, the accurate one-step state transition probability matrix P of cell's number in the buffer is derived, and then cell queue length steady probability distribution can be found. We can compute the accurate buffer capacity below certain cell loss probability. Computer simulation proves that the approach is efficient and exact.

We describe a novel method for scheduling highspeed network switches. The targeted architecture is an input-buffered switch with a non-blocking switch fabric. The input buffers are organized as virtual output queues to avoid head-of-line blocking. The task of the scheduler is to decide when the input ports can forward packets from the virtual output queues to the corresponding output ports. Our Least Choice First (LCF) scheduling method selects the input and output ports to be matched by prioritizing the input ports according to the number of virtual output queues that contain packets: The fewer virtual output queues with packets, the higher- the scheduling priority, of the input port. This way the number- of switch connections and, with it, switch throughput is maximized. Fairness is provided through the addition of a round-robin algorithm. We present two alternative implementations: A central implementation intended for narrow, switches and a distributed implementation based on an iterative algorithm intended for wide switches. The simulation results show that the LCF scheduler outperforms other scheduling methods such as the parallel iterative matcher, iSLIP, and the wave front arbiter.

An analytical performance model for multistage interconnection networks with finite, infinite and zero length buffers

The paper describes a 4 × 4 laser diode optical gate switch made on an InGaAs/GaAs single quantum well GRIN-SCH wafer. The switches were made very compact (only 1.1 × 1.6 mm) by using a Y reflection type optical branching/combining circuit with wide-angle splitting. The light signal launched into an input port is transmitted to an output port through seven gate waveguides and six Y branching circuits. All of the paths between the input and output ports exhibit lossless switching operations when a current of 16 mA (average value) is injected into one gate. The excess loss of the Y branching circuit is estimated to be 0 dB for through coupling and 4 dB for crosscoupling. Good fabrication uniformity of the individual device elements (i.e. the gate waveguide and Y reflection type branching circuit) were confirmed in an area of 10 mm × 10 mm, which was one unit of the photolithography process used in the experiments. However, a significant difference in gain characteristics between the input–output paths in the 4 × 4 switches was observed. The disagreement between the uniformity of the individual elements and the scattering of the path gain characteristics can be explained by the zigzag propagation of the light beam eccentrically launched into the waveguides through the Y reflection type branching circuit.

The discovery of valley degrees of freedom in electronic and classical waves opened the field of valleytronics and offered the prospect for new devices based on valleys. However, the implementation of valley-based devices remains challenging in practice. Here, by taking advantage of the flexibility of phononic crystals in design and fabrication, the realizations of valley devices, or filters, valves, and diverters for acoustic waves are reported. All the devices are configured as the structures of input and output ports bridged by channels. The phononic crystals serving as ports allow the propagation of both valley polarizations, whereas the phononic crystals serving as channels, as they are narrow, only allow the propagation of single polarizations. For valley filters that achieve valley-polarized currents, the bridge channel is simply a straight single phononic crystal, but for valley valves that can turn off the valley-polarized currents, the channel consists of two parts, allowing the propagation of opposite valley polarizations. The valley diverters have one input port, and two output ports, and thus a branched channel, and the three parts in the channel allow the propagation of the same valley polarizations, so that the energy flow can be partitioned. The results may serve as a basis for developing advanced acoustic valley devices.

This paper introduces a three-port DC-DC converter (TPC) designed for enhanced voltage gain applications. The TPC features two input ports, including a bidirectional port for the charging and discharging of a battery. It incorporates a switched inductor to achieve higher voltage gains. The converter is capable of operating in four modes, one of which is a battery-alone mode. Compared to existing topologies, the proposed design significantly reduces input current ripple and ensures a common ground connection between the input and output ports. This configuration makes the TPC particularly suitable for renewable energy applications. The functionality and effectiveness of the proposed converter are validated through an experimental prototype with a power of around <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">400 W</i> . The experiments verified the converter’s dynamic performance during load step changes and mode transitions.

We propose a general design technique for high-performance fault-tolerant networks in multiprocessor systems. The proposed technique called extra link multistage interconnection network (ELMIN) can distribute the load evenly and tolerate faults by providing maximal independent paths at the expense of some additional hardware (extra links), which is much smaller than most of the networks proposed earlier. In this paper, the technique is applied to some specific networks, i.e., the CIN (cube interconnection network) and the d-dilated CIN, to show how to maximize the number of redundant paths. The routing algorithms for the ELMIN have the same simplicity as that of the original MIN. We analyze the performance of the proposed networks and also simulate them along with several others under the buffered and unbuffered packet switching environment. Both analysis and simulation show the high performance of the proposed networks without regard to the presence of faults.

We present theoretical models and numerical results for performance of a multiprocessor network modeled as a ring and as a 2-dim wraparound square lattice of nodes with local processors that generate messages with rate λ per clock cycle and two or, respectively, four output ports/buffers. Two different models are considered. One assumes that the generation rate of a node depends on the intensity of the flow of arriving messages. The other model considers networks with limited buffers. The average queue lengths and average latency are obtained. The results show that the model of independent queues, which is valid for networks with homogeneous activity and infinite buffers, is not applicable, which violates the Jackson theorem.

In loss less interconnection networks such as InfiniBand, congestion control (CC) can be an effective mechanism to achieve high performance and good utilization of network resources. The InfiniBand standard describes CC functionality for detecting and resolving congestion, but the design decisions on how to implement this functionallity is left to the hardware designer. One must be cautious when making these design decisions not to introduce fairness problems, as our study shows. In this paper we study the relationship between congestion control, switch arbitration, and fairness. Specifically, we look at fairness among different traffic flows arriving at a hot spot switch on different input ports, as CC is turned on. In addition we study the fairness among traffic flows at a switch where some flows are exclusive users of their input ports while other flows are sharing an input port (the parking lot problem). Our results show that the implementation of congestion control in a switch is vulnerable to unfairness if care is not taken. In detail, we found that a threshold hysteresis of more than one MTU is needed to resolve arbitration unfairness. Furthermore, to fully solve the parking lot problem, proper configuration of the CC parameters are required.

Performance analysis of packet switches with input and output buffers