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Performance evaluation of a computer using programmable logic units

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Abstract

Abstract The programmable logic unit (PLU) has been proposed to realize a high‐speed operation. The idea is to perform computation obtained by a static data flow scheme using the stepwise arithmetic logics distributed in the memory. This paper describes the configuration of the prototype PLU, the basic concepts of the computation and the synchronization between the PLU and the main control unit (CU). Then theoretical discussions are made on the computation time for the arithmetic and the iterative programs. It is shown that the high‐speed processing is realized by the effects of the parallel computation and of the pipelined computation, mapping many templates of a loop program on the PLU. Furthermore, the multiprogramming for the computer with PLU is proposed to utilize effectively the waiting time for the computation in the PLU. The throughput improvement is indicated by theoertical analysis, comparing the computer using PLU with the traditional sequential computer. Finally, the usefulness of the PLU is demonstrated.

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