Performance Evaluation of Flash Translation Layer Considering Utilization and Dynamic Over-provisioning

Recent consumer devices such as smartphones, smart TVs and tablet PCs adopt NAND flash memory as storage device due to its advantages of small size, reliability, low power consumption, and high performance. The unique characteristics of NAND flash memory require an additional software layer, called flash translation layer (FTL), between traditional file systems and flash memory. In order to reduce the garbage collection cost, FTLs generally try to separate hot and cold data. Previous hot and cold separation techniques monitor the storage access patterns within storage device, or exploit file system hints from host system. This paper proposes a novel clustered page-level mapping, called CPM, which can separate hot and cold data efficiently by allocating different flash memory block groups to different logical address regions. CPM can reduce the FTL map loading overhead during garbage collection and it does not require any high-cost monitoring overhead or host hint. This paper also proposes a K-associative version of CPM, called K-CPM, which allows different logical address regions to share a physical block group in order to achieve high block utilizations. Experimental results show that CPM improves the storage I/O performance by about 54% compared with a previous page-level mapping FTL, and K-CPM further improves the performance by about 19.4% compared with CPM.

In NAND flash-based storage systems, an intermediate software layer called a Flash Translation Layer (FTL) is usually employed to hide the erase-before-write characteristics of NAND flash memory. We propose a novel superblock-based FTL scheme, which combines a set of adjacent logical blocks into a superblock. In the proposed Superblock FTL, superblocks are mapped at coarse granularity, while pages inside the superblock are mapped freely at fine granularity to any location in several physical blocks. To reduce extra storage and flash memory operations, the fine-grain mapping information is stored in the spare area of NAND flash memory. This hybrid address translation scheme has the flexibility provided by fine-grain address translation, while reducing the memory overhead to the level of coarse-grain address translation. Our experimental results show that the proposed FTL scheme significantly outperforms previous block-mapped FTL schemes with roughly the same memory overhead.

Solid state drives (SSDs) implement a log-structured write pattern, where obsolete data remains stored on flash pages until the flash translation layer (FTL) erases them. erase() operations, however, cannot erase a single page, but target entire flash blocks. Since these victim blocks typically store a mix of valid and obsolete pages, FTLs have to copy the valid data to a new block before issuing an erase() operation. This process therefore increases the latencies of concurrent I/Os and reduces the lifetime of flash memory. Data classification schemes identify data pages with similar update frequencies and group them together. FTLs can use this grouping to design garbage collection strategies to find victim blocks that have less valid data with respect to having no data classification, and therefore to significantly reduce the number of additional I/Os. Previous data classification algorithms have been designed without leveraging special features of flash memory and often rely on workload-specific configurations. Our classifier FADaC tunes its parameters online and operates on any given amount of memory by storing additional information within the metadata of flash pages. Additional read() requests for the classification are so few that FADaC reduces the internal flash overhead by up to 45% compared to the best classifier from previous work.

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

Flash memory SSDs pose a well-known challenge, that is, the erase-before-write problem. Researchers try to solve this inherent problem from two different angles by either designing sophisticated Flash Translation Layer (FTL) schemes to postpone and minimize erasures or designing flash-aware buffer management algorithms to absorb unnecessary erasures. Our experimental results show that buffer management inside SSD is necessary and indispensable. Further, based on our observation that TPC and some server workloads have strong temporal locality, this paper proposes a new flash-aware write-buffer management algorithm, called PUD-aware LRU algorithm (PUD-LRU), based on the Predicted average Update Distance (PUD) as the key block replacement criterion on top of log-block FTL schemes. The main idea of PUD-LRU is to differentiate blocks and judiciously destage blocks based on their frequency and recency so as to avoid the unnecessary erasures due to repetitive updates. To take advantage of the characteristics of log-block FTL and increase the erase efficiency, PUD-LRU maximizes the number of valid pages in the destaged block in each erase operation. Our trace-driven experimental results show that the PUD-LRU algorithm can reduce the number of erasures of the state-of-the-art buffer management algorithm BPLRU by up to 42%, and average response time by up to 56%, while reducing the two measures of the state-of-the-art page-mapping FTL scheme DFTL by up to 73% and 75%, respectively.

Loop optimization, made of a sequence of loop transformations, plays an important role in performance improvement in data centric applications. Programs using flash memory are no exception to this, but, under certain conditions careless applications of specific loop transformations might cause unexpected results, due to the characteristics of flash memory and underlying management systems. In this article, we analyze how loop transformations affect the performance in flash translation layers (FTLs). First, we choose four loop structures which have distinct reference patterns and propose a cost model for each structure, reflecting the properties of flash memory. Then, using these cost models, we investigate how loop transformations affect the block associative sector translation (BAST)'s and fully associative sector translation (FAST)'s internal operations and analyze the performance effect of loop transformations experimentally. As a result, we find that some of the major loop transformations cause unexpected performance effects in those major FTLs under certain conditions.

Flash memory is being rapidly deployed as data storage for embedded devices such as PDAs, MP3 players, mobile phones and digital cameras due to its low electronic power, non-volatile storage, high performance, physical stability and portability. The most prominent characteristic of flash memory is that prewritten data can only be dynamically updated via the time consuming erase operation. Furthermore, every block in flash memory has a limited program/erase cycle. In order to manage these issues, the flash memory controller can be integrated with a software module called the flash translation layer (FTL). This paper surveys the state-of-art FTL algorithms. The FTL algorithms can be classified by the complexity of the algorithms: basic and advance. Furthermore, they can be classified by their corresponding tasks: performance enhancement and durability enhancement. The FTL algorithms corresponding to each classification are further broken down into various schemes depending on the methods they adopt. This paper also provides the information of hardware features of flash memory for FTL programmers.

The poor performance of random writes has been a cause of major concern which needs to be addressed to better utilize the potential of flash in enterprise-scale environments. We examine one of the important causes of this poor performance: the design of the flash translation layer (FTL) which performs the virtual-to-physical address translations and hides the erase-before-write characteristics of flash. We propose a complete paradigm shift in the design of the core FTL engine from the existing techniques with our Demand-Based Flash Translation Layer (DFTL) which selectively caches page- level address mappings. Our experimental evaluation using FlashSim with realistic enterprise-scale workloads endorses the utility of DFTL in enterprise-scale storage systems by demonstrating: 1) improved performance, 2) reduced garbage collection overhead and 3) better overload behavior compared with hybrid FTL schemes which are the most popular implementation methods. For example, a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution shows a 78% improvement in average response time (due to a 3-fold reduction in operations of the garbage collector), compared with the hybrid FTL scheme. Even for the well-known read-dominant TPC-H benchmark, for which DFTL introduces additional overheads, we improve system response time by 56%. Moreover, interestingly, when write-back cache on DFTL-based SSD is enabled, DFTL even outperforms the page-based FTL scheme, improving their response time by 72% in Financial trace.

Solid-State Drives (SSDs) have gained acceptance by providing the same block device abstraction as magnetic hard drives, at the cost of suboptimal resource utilisation and unpredictable performance. Recently, Open-Channel SSDs have emerged as a means to obtain predictably high performance, based on a clean break from the block device abstraction. Open-channel SSDs embed a minimal flash translation layer (FTL) and expose their internals to the host. The Linux open-channel SSD subsystem, LightNVM, lets kernel modules as well as user-space applications control data placement and I/O scheduling. This way, it is the host that is responsible for SSD management. But what kind of performance model should the host rely on to guide the way it manages data placement and I/O scheduling? For addressing this question we have defined uFLIP-OC, a benchmark designed to identify the I/O patterns that are best suited for a given open-channel SSD. Our experiments on a Dragon-Fire Card (DFC) SSD, equipped with the OX controller, illustrate the performance impact of media characteristics and parallelism. We discuss how uFLIP-OC can be used to guide the design of host-based data systems on open-channel SSDs.

Solid state drives are becoming more popular for data storage because of their reliability, performance and low power consumption. As the amount of sensitive data stored on these drives increases, the need to securely erase the sensitive information becomes more important. However, this is problematic because the tools and techniques used on traditional hard drives do not always work on solid state drives as a result of differences in the internal architectures. Single file sanitization is highly unreliable and difficult to accomplish on a solid state drive due to wear-leveling and related features. This chapter presents a reliable method for individual file sanitization on solid state drives. The method, called FTLSec, integrates a page-based encryption system in the generic flash translation layer. The efficacy of FTLSec is measured using a FlashSim solid state drive simulator. The results are compared with the well-known FAST flash translation layer scheme and an idealized page-mapped flash translation layer.

Janus-FTL, a recently proposed Flash Translation Layer (FTL) software layer for flash memory storage, has the potential to reduce the worst case write time of flash memory storage by keeping hot data in the page mapping area and cold data in the block mapping area. In this paper, we present the design of the real-time Janus-FTL that guarantees worst case garbage collection cost and write response time. In the proposed FTL, each task needs to decide whether to place its data either in the page mapping area or the block mapping area. A naive optimal placement algorithm, which minimizes the worst case write time, has O(2N) time complexity for N tasks. We propose an algorithm reducing the time complexity from O(2N) to O(N log N). Through experiments, we verify that the real-time Janus-FTL reduces the worst case write time and, as a result, accommodates more real-time tasks than the previous state-of-the-art realtime page mapping FTL.

The performance of flash memory is limited by its “erase-before-write,” and erase operations can only be performed in a much larger unit than write operations. To address these problems, we propose an efficient flash translation layer scheme called BLF: Block List Flash Translation Layer. BLF unites log blocks and physical blocks for servicing update requests. It can avoid uneven erasing and low block utilization. The address translation table of BLF can avoid storing an extra internal mapping table. BLF’s garbage collection method divides the storage zone into three levels: the active zone where hot data are stored, the inactive zone where cold data are stored, and the transitional zone where reclamation block is stored. If invalid blocks can be reclaimed properly and intensively, merging log blocks with physical blocks can be avoided and the amount of operations can be reduced. Finally, we implement an accurate flash simulator to evaluate the efficacy of BLF and compare it with other flash schemes, demonstrating that the improved performance resulting from BLF substantially outperforms other flash schemes.

Characteristics of Sickle Cell Patients with Frequent ED Visits and Hospitalizations: Demographic, Clinical, Laboratory and Psycho-Social Aspects

To evaluate the utility of selective esophageal manometry in clinical practice. Retrospective data from 200 subjects was reviewed. Manometry was considered to be (1) high clinical utility when specific abnormality was identified resulting in therapeutic intervention, (2) low clinical utility when specific abnormality was identified without alteration of therapy, (3) limited clinical utility when manometry was normal. High, low, and limited clinical utility was noted in 47, 40, and 13% of instances. Manometry was of high utility in patients with dysphagia or non-cardiac chest pain (P < 0.05), and low utility in gastroesophageal reflux (P < 0.05). (1) Esophageal manometry has high clinical utility in dysphagia after exclusion of structural disorders; and non-cardiac chest pain after careful exclusion of reflux. (2) Ineffective motility disorder has high association with gastroesophageal reflux disease but low clinical utility except in preoperative assessment for fundoplication. (3) Esophageal manometry is of high utility in clinical practice when used in conjunction with other diagnostic exclusions.

Despite evidence linking domestic violence (DV) exposure with a variety of adverse outcomes, formal programs addressing DV in the pediatric setting are lacking. In order to address DV, St. Christopher's Hospital for Children (SCHC) in Philadelphia, PA developed Children and Mom's Project (CAMP) in 2005. For CAMP, SCHC collaborates with Lutheran Settlement House's Bilingual Domestic Violence Program (BDVP) to screen families for DV and provide such services to those screened positive. This study focused on CAMP's evaluation with the goal to profile the characteristics of DV victims who received DV resources at SCHC, including utilization levels. Data collected between October 2005 and October 2010 on 637 DV victims were retrospectively reviewed and analyzed through descriptive and analytical statistics to assess demographic characteristics, safety markers, and service utilization. Most subjects were female, African American or Hispanic, English-speaking, 18-35 years of age, and reported having one or two dependents. Compared to national statistics of DV victims, our subjects were younger and more likely to be female, African American or Hispanic, single, and with dependents. For each subject, a median of two contacts was made, for a total of 35 minutes of services per day. Subjects who utilized DV services at least thrice, for more than 15 minutes were considered "high utilizers" (31%). Based on two safety variables, "high utilizers" confront more dangerous DV situations than "low utilizers" (&lt;3 contacts, or 15 minutes or less of DV services). Accurate assessments of safety and stability over time were not possible due to inadequacy of the data. Future evaluation of CAMP seeks creation of a survey tool to prospectively assess health and safety outcomes of families receiving DV services.