Performance Improvement using Application-Specific Instructions under Hardware Constraints

This work proposes a hierarchical Design Space Exploration (DSE) for the design of multi-processor platforms targeted to specific applications with strict timing and area constraints. In particular, it considers platforms integrating multiple Application Specific Instruction Set Processors (ASIPs) and each ASIP is automatically synthesized and tuned for a specific set of tasks. The definition of the platform (number of processors and their interconnection) and of the micro-architecture of each single ASIP are tightly coupled. Tasks can be allocated to the different ASIPs only knowing their performance and therefore the ASIP micro-architecture. At the same time an ASIP can be derived only knowing the functionality that it has to implement, i.e. the tasks that are assigned. We break this circular dependency with an iterative hierarchical DSE, applied at platform and micro-architecture level. We evaluate different platforms and micro-architecture alternatives to find a multi-ASIP platform targeted to the input application and able to meet the design constraints. We evaluate our design flow using a MJPEG encoder application.

Chapter 14 - Application Specific Instruction Set Processor for UMTS-FDD Cell Search

In modern SoC designs, more and more application specific instruction-set processors (ASIPs) are used. They enable a trade off between the flexibility due to the software implementation of algorithms and hardware efficiency arising from the ASIP architecture which is optimized with respect to the application. In this paper, it is shown that the total power dissipation could be reduced by distributing the software tasks on several identical ASIP instances although the throughput of a single ASIP would be sufficient for all tasks. In addition, it is shown that for power comparisons of processor instances, the number of executed lines of code is a parameter which gives more insight into power comparisons than the clock rate.

This paper proposes a LDPC (Low Density Parity Check Codes) encoder architecture for DMB-TH based on ASIP (Application Specific Instruction Set Processor). The encoding algorithm is first analyzed and optimized for the ASIP encode, And then the special instruction sets are extracted according to the optimized algorithm. The ASIP architecture uses main processor and coprocessor to get high throughput. This ASIP encoder can support three different code rates (0.4, 0.6 and 0.8) just by different programs and thus is more flexible than other ASIC implementations. Based on XC2V6000, at the max frequency of 117MHz, the max throughput of the encoder can deliver 187Mbps, 206Mbps and 232Mbps for 0.4, 0.6 and 0.8 code rates, respectively.

The development of application specific instruction set processors (ASIP) is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expertise knowledge in different domains: application software development tools, processor hardware implementation, and system integration and verification. This paper presents a retargetable framework for ASIP design which is based on machine descriptions in the LISA language. From that, software development tools can be automatically generated including HLL C-compiler, assembler, linker, simulator and debugger frontend. Moreover, synthesizable HDL code can be derived which can then be processed by standard synthesis tools. Implementation results for a low-power ASIP for DVB-T acquisition and tracking algorithms designed with the presented methodology will be given.

Several techniques have been proposed to reduce the energy consumption of ASIPs (Application-Specific Instruction set Processors). While those techniques can reduce the energy consumption with minimal change in the instruction set (IS), they often fail to exploit the opportunity of designing the entire IS from the energy-efficiency perspective. In this chapter we present an energy-efficient IS synthesis that can comprehensively reduce the energy-delay product (EDP) of ASIPs through optimal instruction encoding, considering both the instruction bitwidth and the dynamic instruction fetch count. Experimental results with a typical embedded RISC processor show that the proposed energy-efficient IS synthesis technique can generate application-specific ISs that are up to 40% more energy-efficient over the native IS for several application benchmarks.

Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instruction encoding schemes for multi-pipe Application Specific Instruction-Set Processors (ASIPs). Forwarding is a popular technique to reduce data hazards in the pipeline to improve performance and is applied in almost all modern processor designs; but it is very area expensive. Instruction encoding schemes have a direct impact on code size; an efficient encoding method can lead to a small instruction width, and hence reducing the code size. We propose application specific techniques to reduce forwarding networks and instruction widths for ASIPs with multiple pipelines. By these design techniques, it is possible to reduce area, code size, and even power consumption (due to reduced area), without costing any performance. Our experiments, on a set of benchmarks using the proposed customization approaches show that, on average, there are 27% savings on area, 30% on leakage power, 16.7% on code size, and at the same time, performance even improves by 4% because of the reduced clock period.

Application specific instruction-set processors (ASIP) are a programmable and flexible alternative of traditional finite state machine (FSM) controlled register-transfer level (RTL) designs for multimode basedband systems. In this paper, we present two ASIPs for small scale multiple-input multiple-output (MIMO) wireless communication systems that demonstrate the soundness and effectiveness of ASIPs for this type of applications. The first ASIP is programmed with multiple MIMO symbol detection algorithms for 4 × 4 systems. The supported detection algorithms are minimum mean-square error (MMSE), two variants of the selective spanning with fast enumeration (SSFE) and K-best list sphere detection (LSD). The second ASIP supports MMSE and zero-forcing dirty paper coding (ZF-DPC) algorithms for a base station (BS) with 4 antennas and for 4 users. Both ASIPs are based on transport triggered architecture (TTA) and are programmed with a retargetable compiler with high level language to meet the time-to-market requirements. The detection and precoding algorithms can be switched in the respective ASIPs based on the error-rate requirements. Depending on the algorithms, MIMO detection ASIP delivers 6.16–66.66 Mbps throughput at a clock frequency of 200 MHz on 90 nm technology. The precoder ASIP provides a throughput of 52.17 and 51.95 Mbps for MMSE and ZF-DPC precoding respectively at a clock frequency of 210 MHz on 90 nm technology.

Multimedia embedded systems require high performance specific computation to process the large among of data that characterizes the multimedia domain at low energy consumption due to battery life. Different optimizations at different levels can considerably improve performance and energy consumption and, after that, the address generation becomes the new performance bottleneck. This paper shows a custom-configurable address generation unit design which extends an application specific instruction set processor (ASIP) to boost the address calculations, improving performance and reducing the energy consumption around 27%. The main innovation of our work resides in a new custom-configurable AGU design which can be automatically implemented and directly connected to the ASIP data-path. This AGU design has a fast interface which allows reading one address in only one cycle and one instruction, and calculates new values without stopping the processor. The presented design can easily be implemented in broad range of ASIPs.

In this paper we research an FPGA based application specific instruction set processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable compilation flow. The toolchain is used to develop an initial processor design, asses the performance and identify the potential bottlenecks. A second design iteration results in a fully optimized ASIP with a VLIW instruction set which allows for high degree of parallelism among the functional units inside the ASIP and has dedicated instructions to accelerate typical packet processing tasks. This way, a single processor is capable of handling the complete throughput of a gigabit Ethernet link. To reach the target of a 10 Gbit/s Ethernet access node several processors operate in parallel in a multicore environment

This chapter discusses the challenges of creating an instruction set simulator (ISS) and system modeling environment for configurable, extensible processors. Processor generation technology is highly automated and is used by designers to create application-specific instruction set processors (ASIPs) targeted to specific application domains. The main challenges for creating an ISS lie in the configurable and extensible nature of the processor, which is tailored by designers at design time, not fixed in advance. Thus simulation models need to be created on the fly when designers have configured a new version of the processor. They need to be created automatically and offer good performance with a variety of use modes. In addition, multiple speed-accuracy trade-offs are necessary to support these various use modes, such as instruction-accurate, cycle-accurate, and pin-level. Furthermore, these ISS models must themselves fit into system modeling and simulation environments, both generated along with the ASIP and commercial third party ESL/EDA tools. Again, multiple use models and trade-offs in simulation scope, speed, and accuracy must be supported. Standards to ease integration and model interoperability in this area have arrived only recently and are just beginning to make life easier for model providers.

An application specific programmable processor (ASIP) suitable for the real-time implementation of matrix computations such as singular value and QR decomposition is presented. The processor incorporates facilities for the issue of parallel instructions and a dual-bus architecture that are designed to achieve high performance. Internally, it uses a CORDIC module to perform arithmetic operations, with pipelining of the internal recursive loop exploited to multiplex the two independent microrotations onto a single piece of hardware. The net result is a flexible processing element whose functionality can be changed under program control, which combines high performance with efficient silicon implementation. This is illustrated through the results of a detailed silicon design study and the applications of the techniques to a combined SVD/QRD system.

The area of hardware/software co-design deals with the design of ASIPs (Application Specific Instruction-set Processors) because they often create the core of an embedded system. Embedded systems with ASIPs are designed for a given task and they have to fulfill several criteria like power consumption, chip size, etc. The success of the design phase is closely related to the existence of good design tools, i.e. tools for ASIP programming and simulation. The simulation itself is very important, because with it we can verify and validate an ASIP design. For this purpose, ASIPs are described using an architecture description language that allows generating the design tools in an automatic way. In this article, we focus on presenting the principles which are used in our fast cycle-accurate interpreted simulator. Beside the simulation speed, we also focus on equivalence assurance between an ASIP simulator and its hardware realization.

Fast Fourier transformation (FFT), a kernel data processing task in communication systems, has been studied intensively for efficient software and hardware implementations. Nowadays, various orthogonal frequency division multiplexing (OFDM)-based wireless communication standards have raised more stringent requirements on both throughput and flexibility for FFT computation. Application-specific instruction set processor (ASIP) has emerged as a promising solution to meet these requirements. This paper presents a novel hierarchical design of an ASIP tailored for FFT. We reconstruct the FFT computation flow into a scalable array structure based on an 8-point butterfly unit (BU). The array structure can easily expand along both the horizontal and vertical dimensions for any-point FFT computation. We incorporate custom register files to reduce memory access and derive a regular data addressing rule accordingly. With the microarchitecture modifications, we extend the instruction set architecture (ISA) with new instructions to accelerate FFT operations. An FFT ASIP is implemented on Tensilica's reconfigurable processor platform. Our FFT ASIP achieves the data throughput of 405.7 Mb/s for 1 K-point FFT, which attains UWB-OFDM specifications. The area of our custom processor is 147 kilo gates and the total processor power consumption is 60.7 mW, which are acceptable compared to several other designs such as application specific integrated circuit, digital signal processing, field-programmable gate array, and other ASIP implementations. We also extend the implementation for up to 8 K-point FFTs, with degraded performance but still meeting the requirements of those communications standards that demand large-size FFT computations.

Underwater acoustic communication systems need Doppler compensation for the server Doppler effects. OFDM (Orthogonal Frequency Division Multiplexing) is widely applied in the underwater acoustic communication systems. FFT is the most computational kernels in the OFDM systems. By exploring the two typical digital signal processing kernels and other basic kernels, an ASIP (Application Specific Instruction set Processor) has been proposed. The proposed composite function unit can reach high MOPS in most DSP kernels with less read/write ports. Also, the proposed composite function unit reduce the memory access and register file access of the FFT, which is the bottleneck of the certain implementation of the FFT. The clock speed of the proposed ASIP can reach up to 600MHz under the CMOS 90nm technology.