Performance models for asynchronous data transfers on consumer Graphics Processing Units

Most Computational Fluid Dynamics (CFD) applications solve the Naiver-Stokes equations using various discretization methods like Finite Difference Method (FDM), Finite Element Method (FEM), Finite Volume Method (FVM), etc. The most compute-intensive process in CFD algorithms is the pressure Poisson solver. Solving the pressure Poisson equation requires the solution of a set of linear simultaneous equations. As the problem size/complexity increases, so does the effort and time invested in solving the equations. This study presents fast and robust iterative solvers and the acceleration of the same using the Graphics Processing Unit (GPU) architecture. Serial versions of the codes are implemented in the C language and the parallelization on GPU is achieved using Compute Unified Device Architecture (CUDA). For this study, a two-dimensional heat conduction problem is considered. FDM is used for discretization. Iterative solvers Conjugate Gradient and Multi Grid methods have been implemented in serial and parallel. The performance enhancement with single GPU and CPU system over a single CPU in terms of computing time is reported. It is seen that multigrid algorithms are superior in convergence and nearly 13 times speed-up has been obtained through GPU acceleration using CUDA, for a grid size of 2048 X 2048. The tests have been done on a cluster with Intel(R) Xeon(R) CPU E5-2670 CPU and NVIDIA K10 GPU.

This work presents an implementation of neocognitron neural network, using a high performance computing architecture based on GPU (graphics processing unit). Neocognitron is an artificial neural network, proposed by Fukushima and collaborators, constituted of several hierarchical stages of neuron layers, organized in two-dimensional matrices called cellular planes. For the high performance computation of face recognition application using neocognitron it was used CUDA (compute unified device architecture) as API (application programming interface) between the CPU and the GPU, from GeForce 8800 GTX of NVIDIA company, with 128 ALU's. As face image databases it was used a face database created at UFSCar, and the CMU-PIE (Carnegie Mellon University pose, illumination and expression) database. The load balancing was achieved through the use of cellular connections as threads organized in blocks, following the CUDA philosophy of development. The results showed the feasibility of this type of device as a massively parallel data processing tool, and that smaller the granularity and the data dependency of the parallel processing, better is its performance.

The density peak (DP) algorithm has been widely used in scientific research due to its novel and effective peak density-based clustering approach. However, the DP algorithm uses each pair of data points several times when determining cluster centers, yielding high computational complexity. In this paper, we focus on accelerating the time-consuming density peaks algorithm with a graphics processing unit (GPU). We analyze the principle of the algorithm to locate its computational bottlenecks, and evaluate its potential for parallelism. In light of our analysis, we propose an efficient parallel DP algorithm targeting on a GPU architecture and implement this parallel method with compute unified device architecture (CUDA), called the ‘CUDA-DP platform’. Specifically, we use shared memory to improve data locality, which reduces the amount of global memory access. To exploit the coalescing accessing mechanism of GPU, we convert the data structure of the CUDA-DP program from array of structures to structure of arrays. In addition, we introduce a binary search-and-sampling method to avoid sorting a large array. The results of the experiment show that CUDA-DP can achieve a 45-fold acceleration when compared to the central processing unit based density peaks implementation.

Turbo Similarity Searching (TSS) is a two phases searching procedure that has been proven by previous works as one of the best searching method on chemical databases. TSS however consumes lots of computation time due to the number of searches and fusion carried out in the second phase of its procedure. Hence, TSS would not be able to cater the increase in the chemical database size due to this limitation. With the emergence of the parallel technology, this research looks into accelerating TSS on the widely-used many-cores i.e. the Graphics Processing Unit (GPU) and multi-cores platform. This would not only solve the computational time issue but also the cost as GPUs can be obtained at a lower cost. Hence, the implementation of TSS will help the medicinal chemist to execute the virtual screening in an accurate and fast manner. This study investigates the best possible method to parallelize TSS via experimentation of three parallel designs; two designs were implemented on GPU platform using the Compute Unified Device Architecture (CUDA) API namely CUDA 1 and CUDA 2 whilst one design was implemented on multi-core platform using OpenMP API. The CUDA 1 design had shown tremendous speedup and low GPU-memory utilization as compared to CUDA 2 design. In general observation, the parallel CUDA 1 was 131 times faster than sequential and 51 times faster than parallel OpenMP. This leads to the conclusion that CUDA 1 design as the best parallel design for TSS.

Many-core framework, represented by Graphic Processing Unit (GPU), has been becoming more popular in scientific computing and data analysis, and Compute Unified Device Architecture (CUDA) allows developers to carry out computation on GPUs more conveniently. Matrix operation is one of the most important application scenarios of GPU computation and CUDA, widely appearing in domains like graph applications and artificial intelligence. This paper focuses on accelerating matrix power operation (MPO) process, which appears in many engineering problems and may be time-consuming when the scale of matrixes is large, with GPUs and CUDA. In this paper, three techniques are used to speed up the MPO process: matrix parallel reduction, matrix parallel multiplication and CUDA dynamic parallelism. The experiments were carried out on NVIDIA RTX 2080 Super and Intel(R) Core(TM) i7-10750H. The code is compiled and executed in Visual Studio 2019 community, the GPU driver version is 461.40, the CUDA version is 11.1, and the NVCC version is 11.1.74. With all three techniques, the MPO process can get hundreds of times speedup compared with the sequential multiplication process executed by Eigen library, even though the code of algorithm is hardly optimized. Moreover, with the number of power increasing, the efficiency of algorithm can be even higher because of the relatively fixed time consumed in data transmission and GPU memory allocation.

Graphics processing units (GPUs) 1 have enjoyed increasing popularity in recent years, which benefits from, for example, general-purpose GPU (GPGPU) for parallel programs and new computing paradigms, such as the Internet of Things (IoT). GPUs hold great potential in providing effective solutions for big data analytics while the demands for processing large quantities of data in real time are also increasing. However, the pervasive presence of GPUs on mobile devices presents great challenges for GPGPU, mainly because GPGPU integrates a large amount of processor arrays and concurrent executing threads (up to hundreds of thousands). In particular, the root causes of performance loss in a GPGPU program can not be revealed in detail by current approaches. In this article, we propose MiC (Multi-level Characterization), a framework that comprehensively characterizes GPGPU kernels at the instruction, Basic Block (BBL), and thread levels. Specifically, we devise Instruction Vectors (IV) and Basic Blocks Vectors (BBV), a Thread Similarity Matrix (TSM), and a Divergence Flow Statistics Graph (DFSG) to profile information in each level. We use MiC to provide insights into GPGPU kernels through the characterizations of 34 kernels from popular GPGPU benchmark suites such as Compute Unified Device Architecture (CUDA) Software Development Kit (SDK), Rodinia, and Parboil. In comparison with Central Processing Unit (CPU) workloads, we conclude the key findings as follows: (1) There are comparable Instruction-Level Parallelism (ILP); (2) The BBL count is significantly smaller than CPU workloads—only 22.8 on average; (3) The dynamic instruction count per thread varies from dozens to tens of thousands and it is extremely small compared to CPU benchmarks; (4) The Pareto principle (also called 90/10 rule) does not apply to GPGPU kernels while it pervasively exists in CPU programs; (5) The loop patterns are dramatically different from those in CPU workloads; (6) The branch ratio is lower than that of CPU programs but higher than pure GPU workloads. In addition, we have also shown how TSM and DFSG are used to characterize the branch divergence in a visual way, to enable the analysis of thread behavior in GPGPU programs. In addition, we show an optimization case for a GPGPU kernel from the bottleneck identified through its characterization result, which improves 16.8% performance.

Based on the principle of QR loop iterations, this paper implements a parallel algorithm based on the hardware of GPU (Graphic Process Unit) by using routines from CUDA (Computer Unified Device Architecture) to find the eigenvalues of general matrices. CPU and GPU computing card form a client-server computing framework. Here, CPU can be regarded as a client and GPU card is considered as a computing server. For the experiment environment, this paper chooses a GPU card with the model of NVIDIA GeForce GTX460 as a server side and a CPU with the model of Intel Core i5-760 quad-core as a client side. Win7 64-bit is selected as the operating system. The parallel implementation consists of two parts:PA H and PA QR. PA H is a procedure that transforms a matrix A into the Hessenberg matrix B. PA QR is the actual parallel algorithm of the QR iterations that is imposed on the Hessenberg matrix B for finding eigenvalues of the general matrix A. The speedup ratio of the proposed algorithm is jarless when the number of iterations becomes greater. The experimental results show that the parallel implementation with CUDA on GPU only makes use of less running time than traditional sequential algorithms. The speedup ratio of PA H is between 1.79 and 7.81. The speedup ratio of PA QR is between 3.24 and 118.9. Especially, when the order of general matrix equals 8192, the amount of iterations becomes 10000. The speedup ratio of the PA-H and the PA QR can run up to 7.81 and 118.9 respectively.

The small slop approximation (SSA) is an accurate method to calculate the electromagnetic (EM) scattering properties of rough surfaces. However, its computational complexity restricts its application to smaller domains and there is always the need for speedup in very large cases using pure central processing units (CPUs) hardware. With the development of graphics processing units (GPUs), more processors are dedicated to perform independent calculations. In addition, NVIDIA introduced a parallel computing platform, compute unified device architecture (CUDA), which provides researchers an easy way to use processors on GPU. To calculate EM scattering properties on GPU, we reformulate the SSA method with CUDA to take advantage of GPU threads. Because each thread executes synchronously and deals with a corresponding point data of rough surface, the CUDA-based SSA method calculates faster than the pure-CPU equivalent. To overcome memory limitations, the data of large rough surface are stored on hard disk. Moreover, a subsidiary thread is used to deal with the process of data transmission between the memory and the hard disk and reduce transmitting time further. The factors, block size, data transfers, and register, are also discussed in the optimization of the CUDA application. Test cases running on a NVIDIA GTX 460 GPU indicate that two orders of magnitude speedup, including file input and output, is obtained with our new formulation.

Watershed analysis, as a fundamental component of digital terrain analysis, is based on the Digital Elevation Model (DEM), which is a grid (raster) model of the Earth surface and topography. Watershed analysis consists of computationally and data intensive computing algorithms that need to be implemented by leveraging parallel and high-performance computing methods and techniques. In this paper, the Multiple Flow Direction (MFD) algorithm for watershed analysis is implemented and evaluated on multi-core Central Processing Units (CPU) and many-core Graphics Processing Units (GPU), which provides significant improvements in performance and energy usage. The implementation is based on NVIDIA CUDA (Compute Unified Device Architecture) implementation for GPU, as well as on OpenACC (Open ACCelerators), a parallel programming model, and a standard for parallel computing. Both phases of the MFD algorithm (i) iterative DEM preprocessing and (ii) iterative MFD algorithm, are parallelized and run over multi-core CPU and GPU. The evaluation of the proposed solutions is performed with respect to the execution time, energy consumption, and programming effort for algorithm parallelization for different sizes of input data. An experimental evaluation has shown not only the advantage of using OpenACC programming over CUDA programming in implementing the watershed analysis on a GPU in terms of performance, energy consumption, and programming effort, but also significant benefits in implementing it on the multi-core CPU.

Graphics Processing Units (GPUs) are massively parallel, many-core processors with tremendous computational power and very high memory bandwidth. With the advent of general purpose programming models such as NVIDIA's CUDA and the new standard OpenCL, general purpose programming using GPUs (GPGPU) has become very popular. However, the GPU architecture and programming model have brought along with it many new challenges and opportunities for compiler optimizations. One such classical optimization is loop unrolling. Current GPU compilers perform limited loop unrolling. In this paper, we attempt to understand the impact of loop unrolling on GPGPU programs. We develop a semi-automatic, compile-time approach for identifying optimal unroll factors for suitable loops in GPGPU programs. In addition, we propose techniques for reducing the number of unroll factors evaluated, based on the characteristics of the program being compiled and the device being compiled to. We use these techniques to evaluate the effect of loop unrolling on a range of GPGPU programs and show that we correctly identify the optimal unroll factors. The optimized versions run up to 70 percent faster than the unoptimized versions.

Purpose: For microdosimetric calculation event-by-event Monte Carlo (MC) simulation is considered the most accurate, but it is very time-consuming. In this work we present an event-by-event MC simulation of low energy electron and proton for accelerated microdosimetric MC simulations on a graphic processing unit (GPU). Methods: The MC simulation of particle was implemented in C and executed on a multi-core CPU, and a commercially available general purpose GPU using the compute unified device architecture (CUDA). Additionally, a hybrid implementation scheme was realized by employing OpenMP and CUDA so that both GPU and multi-core CPU were utilized simultaneously. The two implementation schemes have been tested and compared with the sequential single threaded MC simulation on the CPU. A calculation time comparison was established on the speed-up for a set of benchmarking cases of electron and proton. Results: Dosimetric results were obtained with both the parallel and serial MC codes. A GPU over CPU speed-up of 67.2 and 19.2 times was achieved for 300 eV and 2 keV electron tracks respectively. For proton tracks, the GPU-based code was approximately 5 times faster than the CPU-single-thread code. By incorporating a multi-core CPU and running the MC code simultaneously on the GPU and CPU, an increase of 2%-7% and 20% in the speedup was noticed for electrons and protons tracks respectively. A good dosimetric agreement between the CPU- and GPU-based MC methods was observed for both electrons and proton. Conclusions: A GPU-based MC method for microdosimetric calculations of low energy electron and proton has been presented. The results indicate the capability of our GPU-based implementation for accelerated MC simulations of both electron and proton without loss of accuracy. Lastly, the potential of a hybrid approach by utilizing simultaneously a GPU and a multi-core CPU for further acceleration of MC microdosimetric calculations has been demonstrated.

<strong class="journal-contentHeaderColor">Abstract.</strong> With semiconductor technology gradually approaching its physical and thermal limits, Graphics processing unit (GPU) is becoming an attractive solution in many scientific applications due to their high performance. This paper presents an application of GPU accelerators in air quality model. We endeavor to demonstrate an approach that runs a PPM solver of horizontal advection (HADVPPM) for air quality model CAMx on GPU clusters. Specifically, we first convert the HADVPPM to a new Compute Unified Device Architecture C (CUDA C) code to make it computable on the GPU (GPU-HADVPPM). Then, a series of optimization measures are taken, including reducing the CPU-GPU communication frequency, increasing the size of data computation on GPU, optimizing the GPU memory access, and using thread and block indices in order to improve the overall computing performance of CAMx model coupled with GPU-HADVPPM (named as CAMx-CUDA model). Finally, a heterogeneous, hybrid programming paradigm is presented and utilized with the GPU-HADVPPM on GPU clusters with Massage Passing Interface (MPI) and CUDA. Offline experiment results show that running GPU-HADVPPM on one NVIDIA Tesla K40m and NVIDIA Tesla V100 GPU can achieve up to 845.4x and 1113.6x acceleration. By implementing a series of optimization schemes, the CAMx-CUDA model resulted in a 29.0x and 128.4x improvement in computational efficiency using a GPU accelerator card on a K40m and V100 cluster, respectively. In terms of the single-module computational efficiency of GPU-HADVPPM, it can achieve 1.3x and 19.4x speedup on NVIDIA Tesla K40m GPU and NVIDA Tesla V100 GPU respectively. The multi-GPU acceleration algorithm enables 4.5x speedup with 8 CPU cores and 8 GPU accelerators on V100 cluster.

<strong class="journal-contentHeaderColor">Abstract.</strong> With semiconductor technology gradually approaching its physical and thermal limits, Graphics processing unit (GPU) is becoming an attractive solution in many scientific applications due to their high performance. This paper presents an application of GPU accelerators in air quality model. We endeavor to demonstrate an approach that runs a PPM solver of horizontal advection (HADVPPM) for air quality model CAMx on GPU clusters. Specifically, we first convert the HADVPPM to a new Compute Unified Device Architecture C (CUDA C) code to make it computable on the GPU (GPU-HADVPPM). Then, a series of optimization measures are taken, including reducing the CPU-GPU communication frequency, increasing the size of data computation on GPU, optimizing the GPU memory access, and using thread and block indices in order to improve the overall computing performance of CAMx model coupled with GPU-HADVPPM (named as CAMx-CUDA model). Finally, a heterogeneous, hybrid programming paradigm is presented and utilized with the GPU-HADVPPM on GPU clusters with Massage Passing Interface (MPI) and CUDA. Offline experiment results show that running GPU-HADVPPM on one NVIDIA Tesla K40m and NVIDIA Tesla V100 GPU can achieve up to 845.4x and 1113.6x acceleration. By implementing a series of optimization schemes, the CAMx-CUDA model resulted in a 29.0x and 128.4x improvement in computational efficiency using a GPU accelerator card on a K40m and V100 cluster, respectively. In terms of the single-module computational efficiency of GPU-HADVPPM, it can achieve 1.3x and 19.4x speedup on NVIDIA Tesla K40m GPU and NVIDA Tesla V100 GPU respectively. The multi-GPU acceleration algorithm enables 4.5x speedup with 8 CPU cores and 8 GPU accelerators on V100 cluster.

This paper proposes a parallel ant colony optimization (ACO) for solving quadratic assignment problems (QAPs) on a graphics processing unit (GPU) by combining fast, 2-opt local search in compute unified device architecture (CUDA). In 2-opt for QAP, 2-opt moves can be divided into two groups based on computing cost. In one group, the computing cost is O(1) and in the other group, the computing cost is O(n). We compute these groups of 2-opt moves in parallel by assigning the computations to threads of CUDA. In this assignment, we propose an efficient method that can reduce disabling time in each thread of CUDA. The results show GPU computation with 2-opt produces a speedup of ×24.6 on average, compared to computation with CPU.

Data-parallel accelerator devices such as Graphical Processing Units (GPUs) are providing dramatic performance improvements over even multi-core CPUs for lattice-oriented applications in computational physics. Models such as the Ising and Potts models continue to play a role in investigating phase transitions on small-world and scale-free graph structures. These models are particularly well-suited to the performance gains possible using GPUs and relatively high-level device programming languages such as NVIDIA’s Compute Unified Device Architecture (CUDA). We report on algorithms and CUDA data-parallel programming techniques for implementing Metropolis Monte Carlo updates for the Ising model using bit-packing storage, and adjacency neighbour lists for various graph structures in addition to regular hypercubic lattices. We report on parallel performance gains and also memory and performance tradeoffs using GPU/CPU and algorithmic combinations.