Performance of exhaustive matching for input-queued switches

We describe a novel method for scheduling highspeed network switches. The targeted architecture is an input-buffered switch with a non-blocking switch fabric. The input buffers are organized as virtual output queues to avoid head-of-line blocking. The task of the scheduler is to decide when the input ports can forward packets from the virtual output queues to the corresponding output ports. Our Least Choice First (LCF) scheduling method selects the input and output ports to be matched by prioritizing the input ports according to the number of virtual output queues that contain packets: The fewer virtual output queues with packets, the higher- the scheduling priority, of the input port. This way the number- of switch connections and, with it, switch throughput is maximized. Fairness is provided through the addition of a round-robin algorithm. We present two alternative implementations: A central implementation intended for narrow, switches and a distributed implementation based on an iterative algorithm intended for wide switches. The simulation results show that the LCF scheduler outperforms other scheduling methods such as the parallel iterative matcher, iSLIP, and the wave front arbiter.

On the fairness of scheduling algorithms for input-queued switches

The virtual output queue (VOQ) has been used in input queued and input-output queued packet switches which require switch plane scheduling algorithms to achieve high throughput. However, existing scheduling algorithms such as iSLIP are designed for scheduling fixed size cell units and introduce unfairness in packet latency among VOQs if used for scheduling variable sized packet units. A self-optimized latency (SOL) scheduling algorithm is proposed to deal with scheduling variable-length packets. The SOL is a credit-based scheduling algorithm which assigns a credit flow for each VOQ. During operation, the SOL examines credit flows to grant access to VOQs through the switch plane. Moreover, the SOL also works in conjunction with an average packet length scheduling concept to modify credit flows based on size of packets transferred through the switch plane in order to increase fairness among VOQs. Simulation results show that the SOL scheduling algorithm in a switch plane significantly reduces the packet latency compared to iSLIP scheduling algorithm.

Port partitioning and dynamic queueing for IP forwarding

Results of the design and performance analysis of two new algorithms for efficient and fair scheduling of variable-length frames in a wavelength division multiplexing (WDM)-passive optical network (PON) under the Stanford University aCCESS-Hybrid PON (SUCCESS-HPON) architecture are reported. The WDM-PON under the SUCCESS-HPON architecture has unique features that have direct impacts on the design of scheduling algorithms. First, an optical line terminal (OLT) uses tunable transmitters and receivers that are shared by all the optical network units (ONUs) served by the OLT to reduce the number of expensive dense WDM (DWDM) transceivers. Second, also for cost reduction, ONUs have no local DWDM light sources but use optical modulators to modulate optical continuous wave (CW) bursts provided by the OLT for upstream transmissions. Therefore, the tunable transmitters at the OLT are used for both upstream and downstream transmissions. To provide efficient bidirectional communications between the OLT and the ONUs and guarantee fairness between upstream and downstream traffic, two scheduling algorithms have been designed: 1) batching earliest departure first (BEDF); and 2) sequential scheduling with schedule-time framing (S/sup 3/F). The BEDF is based on the batch scheduling mode where frames arriving at the OLT during a batch period are stored in virtual output queues (VOQs) and scheduled at the end of the batch period. It improves transmission efficiency by selecting the frame with the earliest departure time from a batch of multiple frames, which optimizes the usage of tunable transmitters in scheduling. Considering the high complexity of the optimization process in BEDF, the S/sup 3/F based on the sequential scheduling mode has also been designed as in the original sequential scheduling algorithm proposed earlier. In S/sup 3/F, the authors use VOQs to provide memory space protection among traffic flows and a granting scheme together with schedule-time framing for both upstream and downstream traffic to reduce framing and guard band overhead. Through extensive simulations under various configurations of the tunable transmitters and receivers, it has been demonstrated that both the BEDF and S/sup 3/F substantially improve the throughput and delay performances over the original sequential scheduling algorithm, while guaranteeing better fairness between upstream and downstream traffic.

With growing internet using demands, the need of services at various scales of Quality of Service (QoS) has made appropriate classification of these types of services mandatory. Therefore, the Differentiated Services Architecture has been proposed for service differentiation at various scales of services. DiffServ network is based on traffic classification mechanism. To measure the measurement of network performance of queue mechanism at router is a very crucial and important task. A number of queue algorithms have been proposed to reduce the routing problems in DiffServ network where priority of packets is a major concern for evaluating the network performance. This paper focuses on queue mechanism at edge router which has to select the higher priority packets enter first into the network. The aim of this work is to minimize the number of drop packets at the edge router. The paper considers performance (in terms of no. of packet drop, average end to end delay) comparison of Random Early Detection algorithm (RED) and Virtual Output Queue (VOQ) algorithm in different network conditions using Network Simulator-2.

The overhead associated with reconfiguring a switch fabric in optical packet switches is an important issue in relation to the packet transmission time and can adversely affect switch performance. The reconfiguration overhead increases the mean waiting time of packets and reduces throughput. The scheduling of packets must take into account the reconfiguration frequency. This work proposes an analytical model for input-buffered optical packet switches with the reconfiguration overhead and analytically finds the optimal reconfiguration frequency that minimizes the mean waiting time of packets. The analytical model is suitable for several round-robin (RR) scheduling schemes in which only non-empty virtual output queues (VOQs) are served or all VOQs are served and is used to examine the effects of the RR scheduling schemes and various network parameters on the mean waiting time of packets. Quantitative examples demonstrate that properly balancing the reconfiguration frequency can effectively reduce the mean waiting time of packets.

Input queues have become an attractive switch architecture, since it was shown that a throughput of up to 100% is achievable when a virtual output queue (VOQ) is used. Although schedulers for VOQ switches have been proposed, pipelined schedulers, whose processing requirements increase at most linearly with line speeds, have not yet matured. We introduce CORPS, a pipelined scheduler which allows fair scheduling among input lines of a crossbar high speed switch fabric. By means of a round-robin communication scheme, CORPS achieves scalability to a large number of ports. Moreover, CORPS achieves one scheduling decision per line per slot, by scheduling packets into future slots. The tradeoffs involved are packet delay and utilization.

In recent years, a lot of power allocation algorithms have been proposed to maximize spectral efficiency (SE) and energy efficiency (EE) for the distributed antenna systems (DAS). However, the traditional iterative power allocation algorithms are difficult to be implemented in reality because of their high computational complexity. With the development of machine learning algorithms, it has been proved that the machine learning method has excellent learning ability and low computational complexity, which can approximate the traditional iterative power allocation well and be easily to be implemented in reality. In this paper, we propose a new deep neural network (DNN) model for DAS. From the perspective of machine learning, traditional iterative algorithms can be regarded as a nonlinear mapping between user channel realizations and optimal power allocation schemes. Therefore, we train the DNN to learn the nonlinear mapping between the user channel realizations and the corresponding power allocation schemes based on the traditional iterative algorithm. Then, a power allocation schemes based on DNN method is developed to maximize SE and EE for DAS. The simulation results show that the proposed scheme can not only obtain the almost similar performance as the traditional iterative algorithm, but also reduce much online computational time.

Network-on-Chip (NoC) is becoming a popular solution for communication on System-on-Chips. A router is a major component of NoC which is responsible for handling the communication. Its architecture significantly impacts on the performance of NoC. In this paper, we propose a low latency router architecture based on virtual output queuing (VOQ). The number of pipeline stages of a packet transfer can be reduced to one stage, by using VOQ buffers and speculatively performing switch allocation and switch traversal in parallel. This paper also proposes a multiple VOQ architecture for which each input port maintains multiple queues for each output channel to improve the throughput of the router. We have implemented the proposed router on FPGA and evaluated in terms of communication latency, throughput and hardware amount. The experimental results show that in a 4 × 4 two-dimensional mesh network, the proposed multiple VOQ router reduces the communication latency by 25% and cost of area by 15.6% as compared to the look-ahead speculative virtual channel router.

Chapter 13 - Switching

Combined input-crosspoint buffered (CICB) packet switches have been of research interest in the last few years because of their high performance. These switches provide higher performance than input-buffered (IB) packet switches while requiring the crosspoint buffers run at the same speed as that of the input buffers in IB switches. Recently, it has been shown that CICB switches with one-cell crosspoint buffers, virtual output queues, and simple input and output arbitrations, provide 100% throughput under uniform traffic. However, it is of general interest to know the maximum throughput that a CICB switch, with no speedup, can provide under admissible traffic. This paper analyzes the throughput performance of a CICB switch beyond uniform traffic patterns and shows that a CICB switch with one-cell crosspoint buffers can provide 100% throughput under admissible traffic while using no speedup.

We present a performance comparison of different multi-input queueing ATM switches that are implemented as virtual output queueing (VOQ) switches. We describe six scheduling algorithms and show their average time delay performance levels. Also, we point out the algorithms' hardware complexity.

Input buffered switches with virtual output queues (VOQ) are scalable to very high speeds, but require switch matrix scheduling algorithms to achieve high throughput. Existing scheduling algorithms based on parallel request grant-accept cycles cannot natively support variable length Ethernet packets. A parallel-polled VOQ (PP-VOQ) architecture is proposed that natively supports variable length packets. Small amounts of FIFO buffering within a crossbar are used. Using simulation, the PP-VOQ with buffered crossbar switch is shown to have lower switch delay at high offered loads than an iSLIP switch for both cell and variable-length packet traffic. The PP-VOQ switch does not require internal speed-up or complex reassembly mechanisms. The priority mechanism implemented in both the iSLIP and PP-VOQ switches are demonstrated to provide guaranteed rate and bounded delay for schedulable traffic.

Network communication protocol is a set of rules used by the network designer while designing a packet in computer network. It is a mechanism through which the network and users are connected together and designer can easily expand and manage the capability of network. In this paper, work is presented on a new communication protocol with signaling mechanisms. This protocol is used for a new Virtual Output Queue (VoQ) router architecture by considering 2D mesh topology to support Quality of Service (QoS) requirements between all hardware resources in Network-on-Chip (NoC). This system will be responsible for forwarding the instantaneous information between the neighbor’s routers. With this new protocol, each router will get the present status information of its neighbor’s router in advance. Major issues of routing like static routing and congestion in the routing path will try to avoid by using this protocol.