Physically Unclonable Function Architectures With Scalable Replication and Intrinsic Uniqueness via Wrinkle‐Engineered Quantum Dot Meshes

The Internet of things (IoT) ecosystem has grown exponentially with the convergence of various technologies such as deep learning, sensor systems, and advances in computing platforms. With such a highly pervasive nature of “smart” devices, the nature of data being collected and processed can be increasingly private and require safeguards to ensure the data’s integrity and security. Physically unclonable functions (PUFs) have emerged as a lightweight, viable security protocol in the Internet of Things (IoT) framework. Malicious modeling of PUF architectures has proven to be difficult due to the inherently stochastic nature of PUF architectures. In this work, we show that knowledge of the underlying PUF structure is unnecessary to clone a PUF. We tackle the problem of cloning PUF-based edge nodes in different settings such as unencrypted, encrypted, and obfuscated challenges in an IoT framework. We present a novel non-invasive, architecture-independent, machine learning attack for robust PUF designs and can handle encryption and obfuscation-based security measures on the transmitted challenge response pairs (CRPs). We show that the proposed framework can successfully clone different PUF architectures, including those encrypted using two (2) different encryption protocols in DES and AES and with varying degrees of obfuscation. We also show that the proposed approach outperforms a two-stage brute force attack model. Finally, we offer a machine learning-based countermeasure, a discriminator, which can distinguish cloned PUF devices and authentic PUFs with an average accuracy of 96%. The proposed discriminator can be used for rapidly authenticating millions of IoT nodes remotely from the cloud server.

Recent fourth industrial revolution, industry4.0 results in lot of automation of industrial processes and brings intelligence in many home appliances in the form of IoT, enhances M2M / D2D communication where electronic devices play a prominent role. It is very much necessary to ensure security of those devices. To provide reliable authentication and identification of each device and to abort the counterfeiting from the unauthorized foundries Physical Unclonable Functions (PUFs) emerged as a one of the promising cryptographic hardware security solution. PUF is function, mathematically modeled by using uncontrollable/ unavoidable random variances of the fabrication process of the ICs. These variances can generate unpredictable, random responses can be used to overcome the difficulties such as storing the keys in non-volatile memories (NVMs) in the classical cryptography. A wide variety of PUF architectures such as Arbiter PUFs, Ring oscillator PUFs, SRAM PUFs proposed by authors. But due to its design complexity and low cost, Delay based Arbiter PUFs (D-PUFs) are considering to be a one of the security primitives in authentication applications such as low-cost IoT devices for secure key generation. This paper presents a review on the different types of Delay based PUF architectures proposed by the various authors, sources to exhibit the physical disorders in ICs, methods to estimate the Performance metrics and applications of PUF in different domains.

Communication security is essential for the proper functioning of the Internet of Things. Traditional approaches that rely on cryptographic keys are vulnerable to side-channel attacks. Physical Unclonable Functions (PUFs), leveraging unavoidable and irreproducible variations of integrated circuits to produce responses unique for individual PUF devices, are emerging as promising candidates as security primitives to provide keyless solutions. Before a PUF can be adopted for real applications, the PUF must be thoroughly examined to understand its various properties for its application feasibility. In this paper, we study XOR PUFs for broad ranges of values for circuit architecture parameters. XOR PUFs have been extensively studied, and have been shown to be unable to withstand machine learning attacks for 64-bit XOR PUFs with less than ten component PUFs. Attack methods employed in existing studies need a large number of challenge-response pairs (CRPs), which are obtainable only if the PUF has an open access interface. When PUF-embedded devices equipped with mutual authentication or response obfuscating techniques, it is difficult for attackers to accumulate large numbers of CRPs. With only a small number of accumulated CRPs available to attackers, small size PUFs, like XOR PUFs with a small number of component PUFs and stages, may become resistant to machine learning attacks. Since smaller sizes mean less resource-demanding, it is worthwhile to examine such PUFs which have usually been considered unsafe against attacks. Such are thoughts that have been motivating us in this paper to explore the PUF performances for a wide range of values of the PUF architecture parameters.

Modern embedded electronic devices are gradually becoming an essential part of everyday lives, proving indispensable for daily activities. The growth of the Internet of things (IoT) technology fuels this phenomenon. IoT devices are found everywhere around us – smartphones, smartwatches, home automation, autonomous cars, and medical implants for human bodies. These devices find widespread use in medical imaging, video surveillance as embedded vision, cloud computing platforms, and military applications. Ensuring the reliability and safety of these devices is of prime importance, since these devices store sensitive data. A wide range of such embedded devices is a common target for intellectual property (IP) theft and reverse-engineering attacks by hackers to access confidential information and counterfeit integrated circuits. Physically unclonable functions (PUFs) are innovative hardware defense techniques that promise a fundamental change in our approach to many security problems. PUFs possess desirable properties like low cost, simple architectures, a light weight, versatility, and the valuable advantage of unclonability. This unclonable property is a consequence of intrinsic random variations at the micro- and nanoscale levels in the manufacturing processes and cannot be controlled or removed. This characteristic also serves as a unique fingerprint for the integrated circuit chips, similar to humans. The widespread usage of PUF techniques in security applications makes it imperative for hardware designers to appreciate its working and understand its uses in practice fully. This chapter aims to address these and other topics by presenting a detailed introduction of the concepts, evaluation parameters, and various ramifications of physically unclonable functions. PUF techniques also provide an economical alternative to ciphers and hash functions for secure cryptographic protocols. It is also necessary to provide security of IoT devices, have economic viability, and fit well with embedded devices’ heterogeneous nature. PUF circuits receive challenges as a sequence of bits and generate matching responses called a challenge-response pair, which can be thought of as a secret key or unique fingerprint. It also obviates the need for storing the keys in nonvolatile memories with dedicated protection, which is a costly affair. In this chapter, different PUFs, including optical PUF, delay-based PUFs, weak and strong PUFs, etc., the maturity of this technology, and their various applications are investigated. This chapter also emphasizes critical challenges toward PUF utilization in IoT and related fields and significant future development areas like critical public infrastructure, reconfigurability, and bit-specific reliability. The unique IoT domain protection criteria and how PUFs can be used to fulfill them are also examined. The chapter’s emphasis is on proven and well-understood strategies involving their benefits and shortcomings.

A survey on silicon PUFs

Physical Unclonable Functions (PUFs) act as functions encoded in hardware, which produce a unique output, being referred to as a response, for a specific input, being called a challenge. PUFs provide a varying level of security, and can, therefore, be used in different applications, depending on the number of their available inputoutput pairs, which are referred to as Challenge-Response Pairs (CRPs). For example, a PUF with only a single challenge-response pair can be used for identification, while a PUF with multiple CRPs can be used to provide multiple different session keys for authentication.^{1, 2} In the first case, the response needs to be secret, while, in the second one, responses can be also used without any secrecy, as long as the related CRPs are not used again. Generally, PUFs are vulnerable to modeling and machine learning attacks. In this paper we investigate and show the resiliency of DRAM-based PUFs against Machine Learning (Naive Bayes (NB), Logistic Regression (LR) and Support Vector machine (SVM)) and also Deep Learning (in particular convolutional neural network (CNN) attacks. We are the first to provide a detailed analysis of on-board DRAM startup values for the purpose of generating unique IDs and their vulnerabilities to attacks. We performed our experiments on the Digilent Atlys board (Xilinx Spartan 6 FPGA); using the on-board DRAM memories (MIRA P3R1GE3EGF G8E DDR2). Our results indicates that the 3 startup value-based DRAM PUFs (DRAM1, DRAM2, and DRAM3) are robust against machine learning attacks.

We propose a scheme to prevent the machine learning (ML) attacks against physically unclonable functions (PUFs). A silicon PUF is a security primitive in a semiconductor chip that generates a unique identifier by exploiting device variations. However, some PUF implementations are vulnerable to ML attacks, in which an attacker tries to obtain the mathematical clone of the target PUF to predict its responses. Our scheme adds intentional noise to the responses to disturb ML by an attacker so that the clone fails to be authenticated, while the original PUF can still be correctly authenticated using an error correction code (ECC). The effectiveness of this scheme is not very obvious because the attacker can also use the ECC. We apply the countermeasure to n-XOR arbiter PUFs to investigate the feasibility of the proposed scheme. We explain the relationship between the prediction accuracy of the clone and the number of intentional noise bits. Our scheme can successfully distinguish a clone from the legitimate PUF in the case of 5-XOR PUF.

Physically Unclonable Functions (PUFs) are becoming more widely recognized as tamper-resistant, high-entropy hardware security primitives. Leveraging the intrinsic manufacturing properties of integrated circuits, PUFs provide a lightweight, cost-effective technique for device identification and cryptographic key generation. Despite the existence of various PUF designs and architectures, the ring oscillator (RO) PUF stands out as one of the most notable. This significance is due to its simplicity of implementation and outstanding performance metrics. However, traditional RO-PUFs are often classified as weak PUFs because they support a limited size of input-output combinations. This paper introduces a configurable inversion unit designed to construct a lightweight, robust architecture configurable (RAC) RO-PUF. The proposed unit comprises an XOR gate, an XNOR gate, and a multiplexer. The RACRO-PUF significantly increases the size of generated output bits while efficiently utilizing minimal hardware resources. The performance of the RACRO-PUF stands out in evaluations, recording a uniqueness of 49.78 %, uniformity of 49.42 %, reliability of 97.72 %, and impressive randomness of 98.34 %.

Ensuring secure and energy‐efficient authentication of resource‐constrained devices has become a critical challenge owing to the rapid expansion of the Internet of Things (IoT) ecosystem. Physically unclonable functions (PUFs) that exploit inherent manufacturing variations to generate device‐unique keys have emerged as a promising hardware‐based security primitive. In this study, a PUF architecture is proposed that utilizes multi‐level programming of flash memory capacitors. Reliable and reproducible binary responses are generated across multiple programmed states by extracting flat‐band voltage variations from capacitance–voltage measurements. Performance is evaluated using the uniformity, P ‐value, inter‐Hamming distance, and intra‐Hamming distance, which indicated strong randomness, uniqueness, and stability. To further enhance the entropy and cryptographic strength, a hash‐based message authentication code (HMAC)‐based key derivation function is integrated, which transformed the PUF outputs into high‐entropy pseudorandom keys. The final architecture supported key generation with zero standby power and is compatible with commercially available memory structures, thereby enabling low‐cost and scalable deployment in secure IoT systems. These results highlight the potential of multi‐level memory‐based PUFs as a lightweight and robust solution for next‐generation hardware security.

The increasingly pervasive problem of counterfeiting affects both individuals and industry. In particular, public health and medical fields face threats to device authenticity and patient privacy, especially in the post-pandemic era. Physical unclonable functions (PUFs) present a modern solution using counterfeit-proof security labels to securely authenticate and identify physical objects. PUFs harness innately entropic information generators to create a unique fingerprint for an authentication protocol. This paper proposes a facile protein self-assembly process as an entropy generator for a unique biological PUF. The posited image digitization process applies a deep learning model to extract a feature vector from the self-assembly image. This is then binarized and debiased to produce a cryptographic key. The NIST SP 800-22 Statistical Test Suite was used to evaluate the randomness of the generated keys, which proved sufficiently stochastic. To facilitate deployment on physical objects, the PUF images were printed on flexible silk-fibroin-based biodegradable labels using functional protein bioinks. Images from the labels were captured using a cellphone camera and referenced against the source image for error rate comparison. The deep-learning-based biological PUF has potential as a low-cost, scalable, highly randomized strategy for anti-counterfeiting technology.

A novel configurable ring oscillator PUF with improved reliability using reduced supply voltage

One of the emerging technologies for cryptographic key storage is hardware intrinsic security based on Physical Unclonable Functions (PUFs); a PUF is a physical structure of a device that is hard to clone due to its inherent, device-unique and deep-submicron process variations. SRAM PUF is an example of such technology that is becoming popular. So far, only a little is published about modeling and analysis of their start-up values (SUVs). Reproducing the same start-up behavior every time the chip is powered-on is crucial to produce the same cryptographic key. This paper presents an analytical model for SUVs of an SRAM PUF based on Static Noise Margin (SNM), and reports some industrial measurements to validate the model. Simulation of the impact of different sensitivity parameters (such as variation in power supply, temperature, transistor geometry) has been performed. The results show that out of all sensitivity parameters, variation in threshold voltage is the one with the highest impact. Industrial measurements on real memory devices validate the simulation results.

The proliferation of reconfigurable devices in the Internet of Things (IoT) and cyber-physical systems (CPS) calls for authentication methods that are efficient, scalable, and impose minimal hardware/firmware overhead. While Physical Unclonable Functions (PUFs) and sensor-based fingerprinting have shown promise, existing approaches either require dedicated circuits or rely on external sensors. This work presents the first Deep Learning (DL) methodology to achieve FPGA device fingerprinting exclusively through ubiquitous embedded on-chip monitoring sensors under hardware-driven workloads, without any additional circuitry. Our method exploits the intrinsic physical variability cascade captured by internal temperature and voltage sensors during electronic activity stimulation, using specific hardware implementations (AES, FFT, and matrix multiplication) as controlled stimuli. Through the employment of multi-channel temporal signatures from sensor readouts, we systematically evaluate how hardware implementations and their spatial distribution across the die affect discriminative capacity. Critically, robust identification is demonstrated despite self-calibrated sensors that normalize first-order statistics—a challenge unaddressed in prior sensor-fingerprinting literature, where such normalization typically eliminates discriminative features. Experimental results with 22 Xilinx Artix™-7 FPGAs under real-world conditions achieve near-100% identification accuracy across varying workloads and placements. Moreover, signatures as short as 25 samples are shown to maintain perfect accuracy, enabling microsecond-latency authentication suitable for a wide range of deployment scenarios. The work further provides comprehensive analysis of individual sensor contributions, model explainability and scalability characteristics, positioning this approach as a practical, zero-overhead solution for trusted embedded systems.

In addition to causing trillion-dollar economic losses every year, counterfeiting threatens human health, social equity and national security. Current materials for anti-counterfeiting labelling typically contain toxic inorganic quantum dots and the techniques to produce unclonable patterns require tedious fabrication or complex readout methods. Here we present a nanoprinting-assisted flash synthesis approach that generates fluorescent nanofilms with physical unclonable function micropatterns in milliseconds. This all-in-one approach yields quenching-resistant carbon dots in solid films, directly from simple monosaccharides. Moreover, we establish a nanofilm library comprising 1,920 experiments, offering conditions for various optical properties and microstructures. We produce 100 individual physical unclonable function patterns exhibiting near-ideal bit uniformity (0.492 ± 0.018), high uniqueness (0.498 ± 0.021) and excellent reliability (>93%). These unclonable patterns can be quickly and independently read out by fluorescence and topography scanning, greatly improving their security. An open-source deep-learning model guarantees precise authentication, even if patterns are challenged with different resolutions or devices.

A deep neural network named PUFNet is proposed, which reveals the unreported threats to device authentication systems based on physically unclonable functions (PUFs). We demonstrates that, by employing novel techniques developed in deep learning community, such as ReLU activation function and Xavier initialization technique, PUFNet successfully predicts the responses of double-arbiter PUF (DAPUF) to unseen challenges with probability of 88.4%, which is 21.1% higher than the conventional method. Those results highlight an important fact that PUF-based authentication schemes should be carefully designed considering the rapid evolving machine learning technology.