Post-layout comparison of high performance 64b static adders in energy-delay space

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

Since miniaturization of CMOS has taken place, speed and power are the most important parameters for any circuit, like speed of an adder is a critical parameter in the overall performance of an Arithmetic Logic Unit (ALU). In order to identify the best suitable 2-bit adder in terms of speed, power dissipation, area and leakage current acomparative study of five different kinds of standard 2-bit adder architectures, Ripple Carry (RCA), Carry Look ahead (CLA), Manchester Carry Chain (MCC), Carry Select (CSL) and Kogge Stone (KSA) adders has been done in this paper.The adders are re-designed, implemented and analyzed at supply voltages ranging from 0.6 - 1 V on 28nm CMOS Technology to improve the speed and power. Simulation results for the different adders show that MCC at 0.6V is 32.4% faster than RCA and 15.6% faster than CLA. RCA having minimum transistor count has the least power dissipation and CLA gives minimum leakage current for lower supply voltages, but as the supply voltage increases MCC produces the least leakage current.

A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 /spl mu/m CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V. >

High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic

In electronic applications, better performance of the digital systems can be achieved using a faster adder circuit. This paper shows a modified carry-select adder (CSA) architecture which has low power and reduced area compared to the regular CSA. This high speed CSA is achieved by replacing the existing binary to excess-1 converter (BEC-1) with D-latch enabled CSA. Regular square-root CSA (SQRT CSA) architectures have also been developed and compared with the proposed BEC-1 D-latch enabled CSA. This work evaluates the performance of delay, area, power, and their products for existing and proposed CSA designs. This shows that proposed D-latch CSA structure is better than the regular and modified SQRT CSA and existing Ripple CSA. The proposed CSA architecture requires approximately 86 % fewer gates and 77 % shorter delay than the original CSA designs.

Computational speed of basic data path elements such as adders plays a crucial role in performance of digital and signal processing systems. Among various adder architectures, carry select adder (CSLA) has better performance in terms of speed in comparison with others. However, this merit is accompanied by its high power dissipation and area occupancy due to redundant computing elements used in each stage hence limiting its application. Power dissipation in these adders can be minimized by various low power implementation techniques such as reversible logic gates, multi-V th approach, and adiabatic logic. Among these low power approaches, adiabatic logic proves to be more efficient in comparison with other low power approaches. In the proposed work, 180 nm CMOS technology in CADENCE environment is used to carry out the design and analysis of both conventional and proposed CSLA architectures. Power dissipation in this proposed 8-bit CSLA architecture reduces by about 82% as compared to conventional 8-bit CSLA adder architecture. Further, the computational delay is also reduced when compared with the conventional 8-bit CSLA architecture. It is noteworthy that delay in adiabatic logic circuits greatly depends on frequency of operation [1].

In this paper, a new carry select adder (CSLA) architecture is proposed with a lower area and a higher speed compared to previous CSLAs. The proposed CSLA is a low-area and high-speed design utilizing a new add-one circuit that is used instead of the second ripple carry adder (RCA) with the input carry equal to one (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> =1) inside each group of the basic CSLA. Moreover, to expedite the add operation, a new grouping structure is proposed instead of the basic square-root (SQRT) grouping as well as utilizing a faster RCA in each group. Despite the fact that the proposed CSLA has not attained the lowest power consumption among all existing designs based on the PDK 45nm standard cell library, but it has achieved the lowest area and delay compared to previous CSLAs. Implementation results show that 8 to 33% area reduction and 12 to 44% speed improvement are achieved in the proposed CSLA compared to previous designs.

10 - Improving energy efficiency in next-generation IoT networks with beam adjustment technique

Decades of techno-economic energy policymaking and research have meant evidence from the Social Sciences and Humanities (SSH)—including critical reflections on what changing a society’s relation to energy (efficiency) even means—have been underutilised. In particular, (i) the SSH have too often been sidelined and/or narrowly pigeonholed by policymakers, funders, and other decision-makers when driving research agendas, and (ii) the setting of SSH-focused research agendas has not historically embedded inclusive and deliberative processes. The aim of this paper is to address these gaps through the production of a research agenda outlining future SSH research priorities for energy efficiency. A Horizon Scanning exercise was run, which sought to identify 100 priority SSH questions for energy efficiency research. This exercise included 152 researchers with prior SSH expertise on energy efficiency, who together spanned 62 (sub-)disciplines of SSH, 23 countries, and a full range of career stages. The resultant questions were inductively clustered into seven themes as follows: (1) Citizenship, engagement and knowledge exchange in relation to energy efficiency; (2) Energy efficiency in relation to equity, justice, poverty and vulnerability; (3) Energy efficiency in relation to everyday life and practices of energy consumption and production; (4) Framing, defining and measuring energy efficiency; (5) Governance, policy and political issues around energy efficiency; (6) Roles of economic systems, supply chains and financial mechanisms in improving energy efficiency; and (7) The interactions, unintended consequences and rebound effects of energy efficiency interventions. Given the consistent centrality of energy efficiency in policy programmes, this paper highlights that well-developed SSH approaches are ready to be mobilised to contribute to the development, and/or to understand the implications, of energy efficiency measures and governance solutions. Implicitly, it also emphasises the heterogeneity of SSH policy evidence that can be produced. The agenda will be of use for both (1) those new to the energy-SSH field (including policyworkers), for learnings on the capabilities and capacities of energy-SSH, and (2) established energy-SSH researchers, for insights on the collectively held futures of energy-SSH research.

Carry propagation delay is a big obstacle to improve the addition efficiency in computer system. And the more data bits the operands have, the delay is more serious. As data bits of operand in optical computer can be huge this makes carry delay be very serious. How to decrease or even mitigate carry delay in addition is very important to promote optical computer in numerical computing applications. To improve the addition efficiency, a new method to design and implement optical adder is put forward. Fully considering the relations between the addend and augend based on modified signed-digit (MSD) number system operands, division algorithm is presented. It makes the design and implementation of the adder much easy and feasible. Besides, it also guarantees that no carry delay is introduced in the process of addition. Meanwhile, the architecture of the adder, its implementation as well as the auxiliary electronic circuit are also presented. Experimental results show that the architecture and design of the new MSD adder are correct. It can avoid carry propagation and is much efficient for optical addition operation.

Based on the idea of sharing two adders used in the carry select adder (CSA), a new design of a low-power high-performance adder is presented. The new adder is faster than a ripple carry adder (RCA), but slower than a CSA. On the other hand, its area and power dissipation are smaller than those of a CSA.

Learning from nature for healthcare, energy, and environment

Improvement of energy efficiency has been a major public policy concern in Korea. Investment cost for location of avoidance facility such as nuclear power and radioactive waste management facility, environmental pollution etc could significantly reduced from improvement of energy efficiency. Energy efficiency improvement could be one of good solution to cope with volatile energy market. Korea has been high oversea dependency in fossil fuels supply to meet its energy requirement. Its import dependency on fossil fuels in 1995 and 2000 is respectively 96.8% and 97.2%. The fact that Korea depends heavily on imported energy shows it should make more efforts to promote improvement of energy efficiency. Although Korean Government has supported industrial sector in improvement of energy efficiency, some energy analysts and critics point out that Korea has little progressed in energy efficiency improvement. This paper estimated its energy efficiency and analyzed its improvement with energy Input- Output table 90-95-2000 of Korea. The results are appeared differently. The cross section and time series analysis result of the energy efficiency is that energy elasticity for GDP, energy intensity and induced energy consumption between 1995 and 2000 significantly improved. From 1990 to 1995, energy elasticity for GDP is bigger than 1. It means that energy consumption increased rapidly more than GDP growth rate. This is the evidence that energy efficiency was not improved. Energy intensity of each industrial sector between 1995 and 2000 is lower than in cases of 1990 and 1995. It shows that energy efficiency was improved. As energy intensity of each industry becomes lower, induced energy consumption of economy goes smaller because of interaction among sectors.

Purpose – This paper aims to describe the creation of innovative and intelligent systems to optimise energy efficiency in manufacturing. The systems monitor energy consumption using ambient intelligence (AmI) and knowledge management (KM) technologies. Together they create a decision support system as an innovative add-on to currently used energy management systems. Design/methodology/approach – Energy consumption data (ECD) are processed within a service-oriented architecture-based platform. The platform provides condition-based energy consumption warning, online diagnostics of energy-related problems, support to manufacturing process lines installation and ramp-up phase and continuous improvement/optimisation of energy efficiency. The systems monitor energy consumption using AmI and KM technologies. Together they create a decision support system as an innovative add-on to currently used energy management systems. Findings – The systems produce an improvement in energy efficiency in manufacturing small- and medium-sized enterprises (SMEs). The systems provide more comprehensive information about energy use and some knowledge-based support. Research limitations/implications – Prototype systems were trialled in a manufacturing company that produces mooring chains for the offshore oil and gas industry, an energy intensive manufacturing operation. The paper describes a case study involving energy-intensive processes that addressed different manufacturing concepts and involved the manufacture of mooring chains for offshore platforms. The system was developed to support online detection of energy efficiency problems. Practical implications – Energy efficiency can be optimised in assembly and manufacturing processes. The systems produce an improvement in energy efficiency in manufacturing SMEs. The systems provide more comprehensive information about energy use and some knowledge-based support. Social implications – This research addresses two of the most critical problems in energy management in industrial production technologies: how to efficiently and promptly acquire and provide information online for optimising energy consumption and how to effectively use such knowledge to support decision making. Originality/value – This research was inspired by the need for industry to have effective tools for energy efficiency, and that opportunities for industry to take up energy efficiency measures are mostly not carried out. The research combined AmI and KM technologies and involved new uses of sensors, including wireless intelligent sensor networks, to measure environment parameters and conditions as well as to process performance and behaviour aspects, such as material flow using smart tags in highly flexible manufacturing or temperature distribution over machines. The information obtained could be correlated with standard ECD to monitor energy efficiency and identify problems. The new approach can provide effective ways to collect more information to give a new insight into energy consumption within a manufacturing system.

Highlights on energy efficiency improvements: a case of a small brewery