Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic

Described is a dynamically reconfigurable 8-function logic gate with seven double-gate carbon nanotube field-effect transistors which demonstrates p-type or n-type behaviour depending on the back-gate voltage. Through simulations, the gate is shown to operate at 20 GHz and has been used to build a 1-bit pipelined full adder using physically identical reconfigurable cells

This paper describes a dynamically reconfigurable 8-function logic gate (CNT-DR8F) based on a double-gate carbon nanotube field effect transistor (DG-CNTFET). The design is based on a property specific to this device: ambivalence, enabling p-type or n-type behavior depending on the back-gate voltage. Using available models, CNT-DR8F is simulated and analyzed at 20GHz operation. The authors also give an example functional block (full adder) to show how to construct logic circuits based on the association of physically identical reconfigurable logic cells.

Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independent nor totally dependent. In this work, we consider the supply and ground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supply voltage values are not known exactly, but that only upper/lower bounds on them are known. In this framework, we propose new timing models for logic gates and identify the worst-case voltage configurations for individual gates and for simple paths. We then give an STA technique that provides the worst-case circuit delay taking supply variations into account.

There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage current, dynamic power, and frequency as a function of supply voltage and body bias are derived and verified with SPICE simulation. Given these models, we show how to derive an analytical expression for the optimal trade-off between supply voltage and body bias, given a required clock frequency and duration of operation. The proposed method is then applied to a processor and is compared with DVS alone for workloads obtained using real-time monitoring of processor utilization for four typical applications.

Operation of complementary metal-oxide-semiconductor (CMOS) logic gates at low supply voltages down to 100mV and ring oscillators down to 67mV is experimentally investigated. The measured voltage transfer characteristics of CMOS inverters and logic gates are explained using the subthreshold operation of MOS transistors. Robust control of ring oscillators allows for a tuning range of six decades in frequency with excellent sensitivity as low as 75mV per frequency decade at low voltages in the range from 0.2 to 0.5V, when body biasing of the metal-oxide-semiconductor field-effect transistors (MOSFETs) is also used. For the present state-of-the-art CMOS, the simple digital CMOS cells can operate properly at supply voltages down to 0.2V, but to achieve operation at lower voltages, additional circuitry is needed to maintain the matching between p- and n-MOSFETs, and the circuit complexity increases. Nevertheless, the experiments with ring oscillators demonstrated good performance of CMOS circuits down to the physical limit of two to three times the thermal voltage, while logic gates with stacked transistors need a supply of approximately four to six times the thermal voltage.

Nonlinear dynamics and chaos can be utilized to build reconfigurable and adaptive logic gates. The inherent reconfigurability of these gates has promising security applications. The existing designs of chaos based logic gates have high overhead compared to CMOS gates. In order to make chaos based logic competitive, we need performance metrics to enable optimization of the design. In this work, we propose a metric that will enable circuit designers to optimize the logic gate design based on application specifications. We focus on a particular topology and study how different factors influence its performance and how they can be optimized to reduce overhead. However, the basic idea can be used for chaotic map circuit using other topologies as well. We also propose an enhancement technique to significantly expand the design space which is desirable for security applications.

Quantum-dot Cellular Automata (QCA) is a newly developed paradigm for digital design. It explains how computation can be performed using nano sized quantum dots. One of the trending application of QCA is the design of reversible logic circuits and gates. Reversible logic is a dissipation less digital logic. According to this logic digital circuitry with almost zero power dissipation can be designed. The most important application of reversible logic is quantum computing. Quantum Computation cannot be performed without the use of reversible circuits. A number of reversible gates have been designed and used in quantum computing. The best way to derive the maximum out of reversible computation is to design those gates and circuits using systems which are inherently reversible. This is true for the quantum mechanical systems. For this quantum level designing Quantum-dot Cellular Automata stands as the appropriate choice. It's a nano level based archetype. Performing multiple functions using single circuits has always been the aim of the digital industry researchers. In reversible logic the approach is developing towards designing multifunction gates that can perform a number of functions using a same circuit with some adjustments. This development has however not yet been explored much in QCA. In this paper the majority logic equations for the outputs of a multifunction reversible logic gate are derived and the novel Quantum-dot Cellular Automata design is proposed. Some of the functions of multifunction reversible logic gate are discussed and simulated results using QCA Designer 2.0.3 are shown in the figure.

Shrinking feature sizes, reduced voltages, and higher transistor count of nano-scale silicon chips challenge designers in terms of performance, power consumption, and reliability. This paper investigates the effect of simultaneous use of dynamic voltage and frequency scaling (DVFS) and body biasing (BB) on power consumption, reliability, and performance. An analytical model of reliability as a function of body bias voltage, supply voltage, and frequency is proposed. We derive a three dimensional optimization problem by exploiting proposed reliability model in conjunction with power consumption and performance model. The resulting problem is solved using widely-used geometric optimization to identify optimal supply voltage and body bias voltage and then is validated using accurate simulation. Afterwards, it is demonstrated how joint energy-performance-reliability space optimization method can be used in an adaptive reliability-aware power management systems. Finally, we show that combined soft error aware BB and DVFS is capable of improving power consumption about 30% in comparison to reliability-aware DVFS only for the same level of reliability and performance constraints.

Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power saving by DVS alone is becoming limited as leakage power increases. In this paper, we show how the simultaneous use of adaptive body biasing (ABB) and DVS can be used to reduce power in high-performance processors. Analytical models of the leakage current, dynamic power, and frequency as functions of supply voltage and body bias are derived and verified with SPICE simulation. We then show how to determine the correct trade-off between supply voltage and body bias for a given clock frequency and duration of operation. The usefulness of our approach is evaluated on real workloads obtained using real-time monitoring of processor utilization for four applications. The results demonstrate that application of simultaneous DVS and ABB results in an average energy reduction of 48% over DVS alone.

Submicron-sized mesas of resonant tunneling diodes (RTDs) with split drain contacts have been realized and the current-voltage characteristics have been studied in the bistable regime at room temperature. Dynamically biased, the RTDs show noise-triggered firing of spikelike signals and can act as reconfigurable universal logic gates for small voltage changes of a few millivolt at the input branches. These observations are interpreted in terms of a stochastic nonlinear processes. The logic gate operation shows gain for the fired-signal bursts with transconductance slopes exceeding the thermal limit. The RTD junction can be easily integrated to arrays of multiple inputs and have thus the potential to mimic neurons in nanoelectronic circuits.

A high-performance NOT logic gate (inverter) was constructed by combining two identical metal-insulator-semiconductor field-effect transistors (MISFETs) made on an individual CdS nanobelt (NB). The MISFETs, which used high-κ HfO2 dielectrics as the top-gate insulator layer, show excellent performance, such as low threshold voltage (∼ −0.1 V), a high on/off ratio (∼108), small subthreshold swing (∼65 mV dec−1) and threshold voltage hysteresis (∼30 mV). The supply voltage for the inverter can be as low as 1 V with a voltage gain as high as 14. When the supply voltage is 7 V, the voltage gain is 72, which is the best reported value, as far as we know, for the inverters based on NB/NW n-channel MISFETs. Besides, the inverter can work in a larger input range with highly stable output voltages. Their high output voltages can make full use of the supply voltages, and their low output voltages can be close to zero. NAND and NOR logic gates have been constructed by assembling three such CdS NB MISFETs, which show high performances as well. The operating principle of the inverter is discussed in detail.

Nowadays, the clean and responsive power management circuits for system-on-a-chip (SoC) are demanding. The SoC enters idle mode by lowering the supply voltage, which even though can extend the battery lifetime, severely challenges the operation of all-analog circuits. As supply voltage reaches near-, even sub-threshold region, all-analog low dropout regulator (LDO) which powers the SoC will have a degraded performance. The digital LDO (DLDO) emerges as a promising solution, by replacing the analog circuits with a wide-range-supply compatible digital controller and thus can realize fast response speed without compromising the power consumption. Nevertheless, there are remaining issues such as poor balance between speed and accuracy, and the sensitivity to process, voltage and temperature variations. In this thesis, circuit level innovations are conducted to overcome these limitations. A capacitor-less DLDO is designed featuring a multi-step switching scheme, as well as an adaptive pipeline control with asynchronous clocking, for area- and power-efficient utilization. The measured load transient response is in nanoseconds for a 500 mA step at 0.6-1.0 V input. However, voltage ripple due to undesirable level toggling is observed during multi-step switching. The second prototype eliminates such ripples by adopting a soft multi-step switching technique which enables a more accurate regulation. DLDOs tend to be more sensitive to the supply noise than their analog counterparts. Analog-assisted digital control is thus investigated to enhance the power supply rejection (PSR). As the auxiliary controller, an inverter-based amplifier (IBA) is designed with rail-to-rail common-mode operation and process-variation compensated trip-point control. The IBA-based LDO is designed, and achieves -20 dB PSR in the megahertz range at 0.2 V lowest supply voltage. This LDO pushes the limit of analog control, and is promising to assist the main regulator for PSR enhancement. All developed prototypes in this thesis are implemented using a standard 65-nm CMOS process.

We fabricated GaN SB-MOSFET using the ITO source/drain and gate with very high drain current and low threshold voltage. Furthermore, we tried to check the body bias effect of the GaN SB-MOSFET after forming the ohmic contact to the substrate. We could control threshold voltage by body bias that makes the device more useful. It is applicable to many of electric circuit applications such as logic gate, memory cell transistors, and image sensors, which are potential area for digital GaN UV optoelectronics.

Post-silicon tuning has recently emerged as an important technique to combat large-scale uncertainties (e.g., process variation, device modeling errors, etc) for today's nanoscale circuits. This talk presents a novel Bayesian Model Fusion (BMF) technique for efficient post-silicon performance modeling and tuning of analog and mixed-signal (AMS) circuits. The key idea is to borrow the simulation or measurement data from an early stage (e.g., pre-silicon) to accurately build AMS performance models at a late stage (e.g., post-silicon). The post-silicon models are then used to facilitate efficient tuning of AMS circuits. A circuit example designed in a commercial 32 nm CMOS process is used to demonstrate the efficacy of the proposed post-silicon performance modeling and tuning methodology based on BMF.

Recently, the design and development of nanozyme-based logic gates have received much attention. In this work, by engineering the stability of the nanozyme-catalyzed product, we demonstrated that the chromogenic system of 3, 3′, 5, 5′-tetramethylbenzidine (TMB) can act as a visual output signal for constructing various Boolean logic operations. Specifically, cerium oxide or ferroferric oxide-based nanozymes can catalyze the oxidation of colorless TMB to a blue color product (oxTMB). The blue-colored solution of oxTMB could become colorless by some reductants, including the reduced transition state of glucose oxidase and xanthine oxidase. As a result, by combining biocatalytic reactions, the color change of oxTMB could be controlled logically. In our logic systems, glucose oxidase, β-galactosidase, and xanthine oxidase acted as inputs, and the state of oxTMB solution was used as an output. The logic operation produced a colored solution as the readout signal, which was easily distinguished with the naked eye. More importantly, the study of such a decolorization process allows the transformation of previously designed AND and OR logic gates into NAND and NOR gates. We propose that this work may push forward the design of novel nanozyme-based biological gates and help us further understand complex physiological pathways in living systems.