Power Analysis Attacks and Algorithmic Approaches to their Countermeasures for Koblitz Curve Cryptosystems

Exchange of private information over a public medium must incorporate a method for data protection against unauthorized access. To enhance the data security against the DPA attack in network communication, a dual field ECC processor supporting all finite field operations is proposed. The ECC processor performs hardware designs in terms of functionality, scalability, performance and power consumption. A unified scheme is introduced to accelerate EC arithmetic functions. The hardware is optimized by a very compact Galois field arithmetic unit with fully pipelined technique. A key-blinded technique is designed against power analysis attacks.

Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level

Fully depleted silicon-on-insulator (FD-SOI) technology is renowned for its back-gate bias voltage controllability. It allows devices fabricated with FD-SOI technology to be optimized for low power consumption or high performance with proper back-gate biases, depending on the required application. This article proposes using the back-gate biasing technique in novel countermeasures against power analysis attacks. Theoretical explanations are discussed, and realistic differential power analysis (DPA) attacks, targeting AES-128 encryption on a 65-nm STOB 32-bit RISC-V microcontroller, are conducted to justify the proposed idea. The experimental results show that when compared with applying no bias, applying our first proposal, which involves using forward back-gate bias, not only improves the test device performance but also enhances its resistance to DPA attacks. Moreover, vulnerability to DPA attacks is kept unchanged when a reverse back-gate bias is applied to achieve low power consumption. The DPA resistance is even more vital when combining the back-gate bias technique with a lower supply voltage. The number of power traces required to retrieve the secret key successfully increases by 14.5 times in the best case. Even better DPA resistance can be obtained when the back-gate bias of the targeted microcontroller is dynamically randomized, as suggested by our second proposal of a random dynamic back-gate bias (RDBB). When RDBB is applied, the number of power traces required to retrieve the secret key successfully significantly increases by 33.4 times.

The CMERE algorithm was designed to resist DPA attacks on modular exponentiation. It was implemented and tested at the algorithmic level for different key sizes of the RSA cryptosystems. The strength of CMERE lied on the facts that it could be implemented both on left-to-right and right-to-left binary methods for modular exponentiation without any changes in the original algorithm. Also, the execution of modular exponentiation was completely bit independent making it a very strong countermeasure against simple and differential power analysis attacks. In this paper, we have verified the CMERE algorithm at hardware level using VHDL. During formal verification with VHDL on FPGA, the algorithm was modified for practical implementation. However, the overall strength of the improved CMERE algorithm remains the same as the original algorithm.

Cryptographic systems can potentially suffer from various attacks which are a consequence of vulnearability of side channel information to analysis attacks. The nature of digital circuits is prone to electromagnetic and power analysis (EMA and PA) attacks. Interconnects in cryptographic circuits emanate information through electromagnetic signals which can be exploited using EMA. Complementary Metal Oxide Semiconductor (CMOS) circuits are vulnearable to leak of computational information through leakage and dynamic power consumption. Dynamic power consumption of cryptographic engines is a rich source to sink in the data under process. The hardware implementation of cryptographic algorithms undermine the security of encrypted system against non brute-force-attacks. The attackers collect and analyse the leakage information of cryptographic circuits to detect the secrete key. The parameters sensitivity of the device and circuits make the cryptographic engines vulnearable to fault injection and inherent inconsistency of the circuits. Dynamic and static power comprise two major components of power consumption of digital circuits. Both power components vary with data under process. This exhibits power consumption has data dependency in digital circuits. To make noisy power profile, various countermeasures have been proposed against Differential Power Analysis (DPA) attacks. In this research, false glitch cells is proposed to work as a countermeasure to generate random transitions and power spikes to scramble power profile. The mathematical foundation of security implications of false glitch cells against Correlation Power Analysis (CPA) attacks is investigated. Moreoever, the security efficiency of utilizing false glitch cells is verified with different metrics.

On two DES implementations secure against differential power analysis in smart-cards

In recent years, power analysis attacks have caused increasingly serious security threats on cryptographicalgorithm, to solve this problem different researcher has put forward many solutions, and among them the fixed value masking technology is one of the mostly used due to its lower cost and faster speed. Both theoretical and practical results have shown that the masking method has a good resistance to differential power analysis (DPA) attack. So based on the in-depth study of fixed masking technology, this paper proposed a second order DPA attack (SODPA) with the help of a pre-processing treatment. In the end, we implemented this attack on a fixed value masked AES encryption algorithm running in Mega16. The experimental result shows that, if the mask value is unknown, ordinary DPA cannot recover the right key, while the second order DPA only needs about 500 power curves to get the correct key. In the meantime, the differences between right and wrong keys are very obvious, which strongly proved the validity and practicability of our method.

ABSTRACTIn this paper, a high‐speed, low‐latency, and high‐security hardware‐implemented triple data encryption standard (3DES) cryptographic algorithm is proposed for securing data privacy. In order to achieve a high throughput for the 3DES architecture, the whole circuit is optimized with a 24‐stage pipelined design at first. For breaking the correlation between the processed data and power dissipation of the 3DES circuit against differential power analysis (DPA) attacks, two pseudo‐random number generators (PRNGs) are embedded to randomly alter the number of pipelined stages and data substitution locations within the 3DES circuit, respectively. Under such a circumstance, the proposed 3DES circuit is able to achieve high performance and strong robustness against DPA attacks without causing much overhead. As shown in the results, under the synthesis of SMIC 14‐nm process design kits (PDK), the clock frequency, area, power dissipation, and throughput of the proposed 3DES circuit, respectively, are achieved as 1.2 GHz, 26,435 m2, 21.05 mW, and 64 Gbps. Furthermore, when DPA attacks are executed on the proposed 3DES circuit, the corresponding secret key cannot be revealed even if 2 million plaintexts are enabled. In contrast, only 40,000 plaintexts are adequate to disclose the secret key of a regular pipelined 3DES circuit.

A Differential Power Analysis (DPA) attack is an exploit which overcomes the hardware and software security by analyzing the correlation between electricity usage of a chip in a device and the encryption key. These attacks are non-invasive, leading an intruder to crack a system without leaving any trace. CMOS Technology is prone to DPA attack because of higher power dissipation. A DPA resistant adiabatic technique has been analyzed which has lower power dissipation when compared to the CMOS technology. The conventional Positive Feedback Adiabatic Logic (PFAL) suffers from certain non-adiabatic energy loss. Hence, Energy Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) is proposed which reduces the non-uniform power consumption, preventing information leakage thus securing the system from DPA attacks. Thus the proposed EE-SPFAL is used to design logical circuits such as buffer, OR-XNOR and AND-NAND gate. It is proved that the information leakage in the form of current consumption takes place in PFAL buffer whereas current consumption traces in EE-SPFAL circuits are uniform, depicting the ability of the proposed logic family to resist DPA attack. The simulation was done using Cadence virtuoso 180 nm technologies.

Embedded wireless devices require secure high-performance cryptography in addition to low-cost and low-energy dissipation. This paper presents for the first time a design methodology for security on a VLIW complex DSP-embedded processor core. Elliptic curve cryptography is used to demonstrate the design for security methodology. Results are verified with real dynamic power measurements and show that compared to previous research a 79% improvement in performance is achieved. Modification of power traces are performed to resist simple power analysis attack with up to 39% overhead in performance, up to 49% overheads in energy dissipation, and up to 11% overhead in code size. Simple power analysis on the VLIW DSP core is shown to be more correlated to routine ordering than individual instructions. For the first time, differential power analysis results on a VLIW using real power measurements are presented. Results show that the processor instruction level parallelism and large bus size contribute in making differential power analysis attacks extremely difficult. This research is important for industry since efficient yet secure cryptography is crucial for wireless communication devices.

Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks

Emerging technologies such as Spin-transfer torque magnetic random-access memory (STT-MRAM) are considered potential candidates for implementing low-power, high density storage systems. The vulnerability of such nonvolatile memory (NVM) based cryptosystems to standard side-channel attacks must be thoroughly assessed before deploying them in practice. In this paper, we outline a generic Correlation Power Analysis (CPA) attack strategy against STT-MRAM based cryptographic designs using a new power model. In our proposed attack methodology, an adversary exploits the power consumption patterns during the write operation of an STT-MRAM based cryptographic implementation to successfully retrieve the secret key. In order to validate our proposed attack technique, we mounted a CPA attack on MICKEY-128 2.0 stream cipher design consisting of STT-MRAM cells with Magnetic Tunnel Junctions (MTJs) as storage elements. The results of the experiments show that the STT-MRAM based implementation of the cipher circuit is susceptible to standard differential power analysis attack strategy provided a suitable hypothetical power model (such as the one proposed in this paper) is selected. In addition, we also investigated the effectiveness of state-of-the-art side-channel attack countermeasures for MRAMs and found that our proposed scheme is able to break such protected implementations as well.

Under a simple power leakage model based on Hamming weight, a software implementation of a data-whitening routine is shown to be vulnerable to a first-order Differential Power Analysis (DPA) attack. This routine is modified to resist the first-order DPA attack, but is subsequently shown to be vulnerable to a second-order DPA attack. A second-order DPA attack that is optimal under certain assumptions is also proposed. Experimental results in an ST16 smartcard confirm the practicality of the first and second-order DPA attacks.

Side-channel attacks, particularly differential power analysis (DPA) attacks, are efficient ways to extract secret keys of the attacked devices by leaked physical information. To resist DPA attacks, hiding and masking methods are commonly used, but it usually resulted in high area overhead and performance degradation. In this brief, a DPA countermeasure circuit based on digital controlled ring oscillators is presented to efficiently resist the first-order DPA attack. The implementation of the critical S-box of the advanced encryption standard (AES) algorithm shows that the area overhead of a single S-box is about 19% without any extra delay in the critical path. Moreover, the countermeasure circuit can be mounted onto different S-box implementations based on composite field or look-up table (LUT). Based on our approach, a DPA-resistant AES chip can be proposed to maintain the same throughput with less than 2K extra gates.

We present a high-speed public-key cryptoprocessor that exploits three-level parallelism in Elliptic Curve Cryptography (ECC) over GF(2 n ). The proposed cryptoprocessor employs a Parallelized Modular Arithmetic Logic Unit (P-MALU) that exploits two types of different parallelism for accelerating modular operations. The sequence of scalar multiplications is also accelerated by exploiting Instruction-Level Parallelism (ILP) and processing multiple P-MALU instructions in parallel. The system is programmable and hence independent of the type of the elliptic curves and scalar multiplication algorithms. The synthesis results show that scalar multiplication of ECC over GF(2163) on a generic curve can be computed in 20 and 16 μs respectively for the binary NAF (Non-Adjacent Form) and the Montgomery method. The performance can be accelerated furthermore on a Koblitz curve and reach scalar multiplication of 12 μs with the TNAF (τ-adic NAF) method. This fast performance allows us to perform over 80,000 scalar multiplications per second and to enhance security in wireless mobile applications.